diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-06-15 13:55:03 +0200 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2021-08-02 14:59:57 +0000 |
| commit | 29924b24fa65e9dad6813ee31968b85e996ddd11 (patch) | |
| tree | 454859e8b904dc94f268bb2166748174c795a444 /src/soc/intel/broadwell/memmap.c | |
| parent | 6672dff0887678fb2f36663d0175d9a88f3de72f (diff) | |
soc/intel/broadwell: Rename `SA_DEV_ROOT`
For consistency with Haswell, rename this macro to `HOST_BRIDGE`.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I4319f04c67aec8df118fa539e00c7328128f0700
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55528
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/broadwell/memmap.c')
| -rw-r--r-- | src/soc/intel/broadwell/memmap.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index f7e58af598..b467dc0a38 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -19,7 +19,7 @@ static uintptr_t dpr_region_start(void) * 1 MiB alignment and reports the TOP of the range, the base * must be calculated from the size in MiB in bits 11:4. */ - uintptr_t dpr = pci_read_config32(SA_DEV_ROOT, DPR); + uintptr_t dpr = pci_read_config32(HOST_BRIDGE, DPR); uintptr_t tom = ALIGN_DOWN(dpr, 1 * MiB); /* Subtract DMA Protected Range size if enabled */ @@ -36,8 +36,8 @@ void *cbmem_top_chipset(void) void smm_region(uintptr_t *start, size_t *size) { - uintptr_t tseg = pci_read_config32(SA_DEV_ROOT, TSEG); - uintptr_t bgsm = pci_read_config32(SA_DEV_ROOT, BGSM); + uintptr_t tseg = pci_read_config32(HOST_BRIDGE, TSEG); + uintptr_t bgsm = pci_read_config32(HOST_BRIDGE, BGSM); tseg = ALIGN_DOWN(tseg, 1 * MiB); bgsm = ALIGN_DOWN(bgsm, 1 * MiB); |