intel/baytrail,broadwell: Move stage cache support function

Let garbage-collection take care of stage_cache_external_region()
when it is not needed and move implementation to a suitable file
already building for needed stages.

Change-Id: Ia6adcc0c8bf6d4abc095ac669aaae876b33ed0f3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34669
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 16 insertions, 1 deletions

diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c
index 836fda8b5d..7c53fa6468 100644
--- a/src/soc/intel/broadwell/memmap.c
+++ b/src/soc/intel/broadwell/memmap.c
@@ -15,11 +15,14 @@
 
 #define __SIMPLE_DEVICE__
 
-#include <device/pci_ops.h>
 #include <cbmem.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include <soc/pci_devs.h>
 #include <soc/systemagent.h>
+#include <soc/smm.h>
+#include <stage_cache.h>
+#include <stdint.h>
 
 static uintptr_t dpr_region_start(void)
 {
@@ -42,3 +45,15 @@ void *cbmem_top(void)
 {
 	return (void *) dpr_region_start();
 }
+
+void stage_cache_external_region(void **base, size_t *size)
+{
+	/* The ramstage cache lives in the TSEG region.
+	 * The top of RAM is defined to be the TSEG base address. */
+	u32 offset = smm_region_size();
+	offset -= CONFIG_IED_REGION_SIZE;
+	offset -= CONFIG_SMM_RESERVED_SIZE;
+
+	*base = (void *)(cbmem_top() + offset);
+	*size = CONFIG_SMM_RESERVED_SIZE;
+}