diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2017-02-16 11:36:16 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-02-20 04:44:22 +0100 |
| commit | c97e042a9bda9994409869369e1cbda551dc65cf (patch) | |
| tree | 42f7a288dbcc63e953a82f7c3ed21b6ec6bba0f6 /src/soc/intel/broadwell/lpc.c | |
| parent | ee6a612eb2edb32a55ee92c6fdfcdc474c6b21f1 (diff) | |
lynxpoint/broadwell: fix PCH power optimizer
Setting both bits 27 and 7 of PCH register PMSYNC_CFG (PMSYNC
Configuration; offset 0x33c8) causes pre-OS display init to fail
on HSW-U/Lynxpoint and BDW-U ChromeOS devices when the VBIOS/GOP
driver is run after the register is set. A re-examination of
Intel's reference code reveals that bit 7 should be set for the
LP PCH, and bit 27 for non-LP, but not both simultaneously.
The previous workaround was to disable the entire power optimizer
section via a Kconfig option, which isn't ideal.
Test: unset bit 27 of PMSYNC_CFG and boot google/lulu,
observe functional pre-OS video output
Change-Id: I446e169d23dd446710a1648f0a9b9599568b80aa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18385
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc/intel/broadwell/lpc.c')
| -rw-r--r-- | src/soc/intel/broadwell/lpc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index c1600c5370..610b9772ee 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -262,7 +262,7 @@ static const struct reg_script pch_pm_init_script[] = { REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3354, 0x00000001), /* Power Optimizer */ REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x08000000), - REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x08000080), + REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x00000080), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b10, 0x0000883c), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b14, 0x1e0a4616), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b24, 0x40000005), |