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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-11 08:45:40 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-28 22:52:14 +0000
commitabddb1fff0262321120e9a82fd00e0c4b6960bbf (patch)
treee832681ed9b1490c47c7f718f22bc119b2bec4b8 /src/soc/intel/broadwell/include
parentd53fd704f252ffde35c8bf2f2b16260edce76e79 (diff)
intel/haswell,broadwell: Rename EMRR to PRMRR
The MSRs were already named as PRMRR in broadwell, just mismatching with the rest of the code. All later devices use the names PRMRR and UNCORE_PRMRR for these MSRs. Reflect the name change in structures and local variables. Change-Id: Id825ba2c083d0def641dd9bf02d3b671d85b1e35 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34825 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/broadwell/include')
-rw-r--r--src/soc/intel/broadwell/include/soc/msr.h2
-rw-r--r--src/soc/intel/broadwell/include/soc/smm.h8
2 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h
index e8e3aa281c..9e196c16b5 100644
--- a/src/soc/intel/broadwell/include/soc/msr.h
+++ b/src/soc/intel/broadwell/include/soc/msr.h
@@ -87,6 +87,6 @@
/* MTRR_CAP_MSR bits */
#define SMRR_SUPPORTED (1<<11)
-#define EMRR_SUPPORTED (1<<12)
+#define PRMRR_SUPPORTED (1<<12)
#endif
diff --git a/src/soc/intel/broadwell/include/soc/smm.h b/src/soc/intel/broadwell/include/soc/smm.h
index fece06dd63..1cc65a53fa 100644
--- a/src/soc/intel/broadwell/include/soc/smm.h
+++ b/src/soc/intel/broadwell/include/soc/smm.h
@@ -27,10 +27,10 @@ struct smm_relocation_params {
u32 ied_size;
msr_t smrr_base;
msr_t smrr_mask;
- msr_t emrr_base;
- msr_t emrr_mask;
- msr_t uncore_emrr_base;
- msr_t uncore_emrr_mask;
+ msr_t prmrr_base;
+ msr_t prmrr_mask;
+ msr_t uncore_prmrr_base;
+ msr_t uncore_prmrr_mask;
/* The smm_save_state_in_msrs field indicates if SMM save state
* locations live in MSRs. This indicates to the CPUs how to adjust
* the SMMBASE and IEDBASE */