diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2014-10-30 15:21:13 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-14 12:12:36 +0200 |
| commit | b22765e0c76e909fe8dc74b9f8f86fc65f278c5e (patch) | |
| tree | 1e332c8b7d73758b709fe61f76580456eb97f6ee /src/soc/intel/broadwell/include | |
| parent | 6c220eacbd42c6134d6520f2956a02a9bd253c9f (diff) | |
broadwell: Remove TPM device from lpc.asl
This is not a standard feature so it should be included by the
mainboard if it is actually present in a system.
BUG=chrome-os-partner:33385
BRANCH=samus,auron
TEST=build and boot on samus
CQ-DEPEND=CL:226663, CL:226664
Change-Id: Id4d0e5ed243dcb95e64fb8c848667f651b75aa4e
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 8909913f5c11c5805c77a3373859634b02a301e2
Original-Change-Id: Ib7c171a5a007a2dddfb3d80341c6dc488e383e99
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/226662
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9470
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/broadwell/include')
| -rw-r--r-- | src/soc/intel/broadwell/include/soc/nvs.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index 195dd43c3e..2f835c88ac 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -44,7 +44,7 @@ typedef struct { u8 tcrt; /* 0x10 - Critical Threshold */ u8 tpsv; /* 0x11 - Passive Threshold */ u8 tmax; /* 0x12 - CPU Tj_max */ - u8 tpmp; /* 0x13 - TPM Present */ + u8 unused1; /* 0x13 - Unused */ u8 s5u0; /* 0x14 - Enable USB in S5 */ u8 s3u0; /* 0x15 - Enable USB in S3 */ u8 s33g; /* 0x16 - Enable 3G in S3 */ @@ -54,7 +54,7 @@ typedef struct { u32 cbmc; /* 0x1d - 0x20 - Coreboot Memory Console */ u32 pm1i; /* 0x21 - 0x24 - PM1 wake status bit */ u32 gpei; /* 0x25 - 0x28 - GPE wake status bit */ - u8 rsvd3[215]; + u8 unused[215]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; |