diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2014-12-12 10:52:34 -0800 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-04-15 21:46:07 +0200 |
| commit | ab1e96a099c5197419308ed40d4fd06507b46ec2 (patch) | |
| tree | 7cf1740a87a8ce22954fe75c1c003986b900473a /src/soc/intel/broadwell/include | |
| parent | cb12f65931aa0bbc30c0e578c988452be70714ed (diff) | |
broadwell: Fixes for _SWS support
- These should be 64bit values so when they try to return -1
it is interpreted properly by the kernel.
- The GPE value needs to be reset at the start so it does not
return stale data from a previous resume.
- If a GPE register is zero the value should only be updated
if it has not yet found a set bit.
BUG=chrome-os-partner:34532
BRANCH=samus,auron
TEST=build and boot on samus, suspend/resume with various
wake sources and ensure the reported _SWS values are correct
in every case.
Original-Change-Id: Ic6897f20ad2f321f3566694c032b75a3db120556
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/235012
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit be3c79b87b81563f744eb885708a52730debaccb)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I801c6e4f90dde0f5f69685f987a9831ee5e99e4a
Reviewed-on: http://review.coreboot.org/9699
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/broadwell/include')
| -rw-r--r-- | src/soc/intel/broadwell/include/soc/nvs.h | 21 |
1 files changed, 10 insertions, 11 deletions
diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index 2f835c88ac..0f1e63a67a 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -44,17 +44,16 @@ typedef struct { u8 tcrt; /* 0x10 - Critical Threshold */ u8 tpsv; /* 0x11 - Passive Threshold */ u8 tmax; /* 0x12 - CPU Tj_max */ - u8 unused1; /* 0x13 - Unused */ - u8 s5u0; /* 0x14 - Enable USB in S5 */ - u8 s3u0; /* 0x15 - Enable USB in S3 */ - u8 s33g; /* 0x16 - Enable 3G in S3 */ - u8 lids; /* 0x17 - LID State */ - u8 pwrs; /* 0x18 - AC Power State */ - u32 obsolete_cmem; /* 0x19 - 0x1c - CBMEM TOC */ - u32 cbmc; /* 0x1d - 0x20 - Coreboot Memory Console */ - u32 pm1i; /* 0x21 - 0x24 - PM1 wake status bit */ - u32 gpei; /* 0x25 - 0x28 - GPE wake status bit */ - u8 unused[215]; + u8 s5u0; /* 0x13 - Enable USB in S5 */ + u8 s3u0; /* 0x14 - Enable USB in S3 */ + u8 s33g; /* 0x15 - Enable 3G in S3 */ + u8 lids; /* 0x16 - LID State */ + u8 pwrs; /* 0x17 - AC Power State */ + u32 cmem; /* 0x18 - 0x1b - CBMEM TOC */ + u32 cbmc; /* 0x1c - 0x1f - Coreboot Memory Console */ + u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */ + u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */ + u8 unused[208]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; |