diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-06-04 14:13:50 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-11-10 22:41:19 +0000 |
| commit | 95755dd65d18955e375345f06da7966f137e7d62 (patch) | |
| tree | 4b26c92e911d09bd4b8443345b385ddca54b5f05 /src/soc/intel/broadwell/include | |
| parent | 2abbe467658a8e4479c381330e85e126c8f42a90 (diff) | |
soc/intel/broadwell: Use common INTEL_SB SPI code
Change-Id: Id906733ac3719c8d6835aad52ca87beb81b5771d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/broadwell/include')
| -rw-r--r-- | src/soc/intel/broadwell/include/soc/spi.h | 28 |
1 files changed, 0 insertions, 28 deletions
diff --git a/src/soc/intel/broadwell/include/soc/spi.h b/src/soc/intel/broadwell/include/soc/spi.h index 5ad62fd19d..f3572570ea 100644 --- a/src/soc/intel/broadwell/include/soc/spi.h +++ b/src/soc/intel/broadwell/include/soc/spi.h @@ -23,7 +23,6 @@ #define SPIBAR_OFFSET 0x3800 #define SPIBAR8(x) RCBA8(x + SPIBAR_OFFSET) -#define SPIBAR16(x) RCBA16(x + SPIBAR_OFFSET) #define SPIBAR32(x) RCBA32(x + SPIBAR_OFFSET) /* Registers within the SPIBAR */ @@ -31,15 +30,6 @@ #define SPIBAR_FDOC 0xb0 #define SPIBAR_FDOD 0xb4 -#define SPI_PRR_MAX 5 -#define SPI_PRR(x) (0x74 + ((x) * 4)) -#define SPI_PRR_SHIFT 12 -#define SPI_PRR_MASK 0x1fff -#define SPI_PRR_BASE_SHIFT 0 -#define SPI_PRR_LIMIT_SHIFT 16 -#define SPI_PRR_WPE (1 << 31) -#define SPI_PRR_RPE (1 << 15) - #define SPIBAR_PREOP 0x94 #define SPIBAR_OPTYPE 0x96 #define SPIBAR_OPMENU_LOWER 0x98 @@ -83,23 +73,5 @@ #define SPIBAR_HSFS 0x04 /* SPI hardware sequence status */ #define SPIBAR_HSFS_FLOCKDN (1 << 15)/* Flash Configuration Lock-Down */ -#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ -#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ -#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ -#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ -#define SPIBAR_HSFC 0x06 /* SPI hardware sequence control */ -#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) -#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ -#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ -#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ -#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ -#define SPIBAR_FADDR 0x08 /* SPI flash address */ -#define SPIBAR_FDATA(n) (0x10 + (4 * n)) /* SPI flash data */ -#define SPIBAR_SSFS 0x90 -#define SPIBAR_SSFS_ERROR (1 << 3) -#define SPIBAR_SSFS_DONE (1 << 2) -#define SPIBAR_SSFC 0x91 -#define SPIBAR_SSFC_DATA (1 << 14) -#define SPIBAR_SSFC_GO (1 << 1) #endif |