diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2018-02-19 17:33:48 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-03-01 16:10:15 +0000 |
| commit | 81a6f109bab8f58984603fbd534e2548be290480 (patch) | |
| tree | a0b788ef08d7134dd4e22f4169b8d0caddc34b45 /src/soc/intel/broadwell/include | |
| parent | e85e0f57acf1b1dfe86b54689cf89659bfd94a54 (diff) | |
soc/intel/broadwell: Enable VT-d and X2APIC
We use the usual static addresses 0xfed90000/0xfed91000 for the GFX
IOMMU and the general IOMMU respectively. These addresses have to be
configured in MCHBAR registers and reserved from the OS.
Change-Id: I7afcce0da028a160174db2cf6b4b6735bcd59165
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/broadwell/include')
| -rw-r--r-- | src/soc/intel/broadwell/include/soc/iomap.h | 6 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/include/soc/lpc.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/include/soc/pci_devs.h | 5 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/include/soc/systemagent.h | 7 |
4 files changed, 21 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/include/soc/iomap.h b/src/soc/intel/broadwell/include/soc/iomap.h index fe8e78b1e2..96b2c1fa45 100644 --- a/src/soc/intel/broadwell/include/soc/iomap.h +++ b/src/soc/intel/broadwell/include/soc/iomap.h @@ -39,6 +39,12 @@ #define HPET_BASE_ADDRESS 0xfed00000 +#define GFXVT_BASE_ADDRESS 0xfed90000ULL +#define GFXVT_BASE_SIZE 0x1000 + +#define VTVC0_BASE_ADDRESS 0xfed91000ULL +#define VTVC0_BASE_SIZE 0x1000 + #define ACPI_BASE_ADDRESS 0x1000 #define ACPI_BASE_SIZE 0x100 diff --git a/src/soc/intel/broadwell/include/soc/lpc.h b/src/soc/intel/broadwell/include/soc/lpc.h index 4fb0d903f2..5cca961bfe 100644 --- a/src/soc/intel/broadwell/include/soc/lpc.h +++ b/src/soc/intel/broadwell/include/soc/lpc.h @@ -86,4 +86,7 @@ #define PMIR_CF9LOCK (1 << 31) #define PMIR_CF9GR (1 << 20) +#define LPC_IBDF 0x6C /* I/O APIC bus/dev/fn */ +#define LPC_HnBDF(n) (0x70 + n * 2) /* HPET n bus/dev/fn */ + #endif diff --git a/src/soc/intel/broadwell/include/soc/pci_devs.h b/src/soc/intel/broadwell/include/soc/pci_devs.h index 59c64ce6c5..0880353999 100644 --- a/src/soc/intel/broadwell/include/soc/pci_devs.h +++ b/src/soc/intel/broadwell/include/soc/pci_devs.h @@ -112,4 +112,9 @@ #define PCH_DEV_SATA2 _PCH_DEV(LPC, 5) #define PCH_DEV_THERMAL _PCH_DEV(LPC, 6) +#define PCH_IOAPIC_PCI_BUS 250 +#define PCH_IOAPIC_PCI_SLOT 31 +#define PCH_HPET_PCI_BUS 250 +#define PCH_HPET_PCI_SLOT 15 + #endif diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h index 125ba47f4c..92e79cc99a 100644 --- a/src/soc/intel/broadwell/include/soc/systemagent.h +++ b/src/soc/intel/broadwell/include/soc/systemagent.h @@ -74,6 +74,11 @@ #define D_LCK (1 << 4) #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) +#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ +#define DMAR_LCKDN (1 << 31) +#define PRSCAPDIS (1 << 2) #define MESEG_BASE 0x70 /* Management Engine Base. */ #define MESEG_LIMIT 0x78 /* Management Engine Limit. */ @@ -95,7 +100,9 @@ #define MCHBAR_PEI_VERSION 0x5034 #define BIOS_RESET_CPL 0x5da8 +#define GFXVTBAR 0x5400 #define EDRAMBAR 0x5408 +#define VTVC0BAR 0x5410 #define MCH_PAIR 0x5418 #define GDXCBAR 0x5420 |