diff options
| author | Kane Chen <kane.chen@intel.com> | 2014-08-28 17:05:06 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-03-27 06:36:37 +0100 |
| commit | 46134728402601abc85a6a9ee01d37f0d50cc705 (patch) | |
| tree | a683c5169e1310ac0ba0615070e500e872948d63 /src/soc/intel/broadwell/cpu.c | |
| parent | 841c9da270c80b121d9d9080f3c15a982fcd9ed4 (diff) | |
broadwell: Fix some errors in selftest
1. Fixed some errors in selftest compare to reference.
2. Some WA steps for xhci in sleep trap is only for lpt.
BUG=chrome-os-partner:28234
TEST=compile ok, run selftest on auron to verify
boot to OS
BRANCH=None
Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Change-Id: Iaccb087581d5f51453614246bf80132fcb414131
Original-Reviewed-on: https://chromium-review.googlesource.com/215646
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Kane Chen <kane.chen@intel.com>
Original-Tested-by: Kane Chen <kane.chen@intel.com>
(cherry picked from commit 97761b4ad3073fff89aabce3ef4f763383ca5cad)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I2b1d5be4f8a13eb00009a36a199520cd35a67abf
Reviewed-on: http://review.coreboot.org/8971
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/broadwell/cpu.c')
| -rw-r--r-- | src/soc/intel/broadwell/cpu.c | 26 |
1 files changed, 0 insertions, 26 deletions
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 8e05998c19..1f2ee0d7ba 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -103,32 +103,6 @@ static const u8 power_limit_time_msr_to_sec[] = { [0x11] = 128, }; -u32 cpu_family_model(void) -{ - return cpuid_eax(1) & 0x0fff0ff0; -} - -u32 cpu_stepping(void) -{ - return cpuid_eax(1) & 0xf; -} - -/* Dynamically determine if the part is ULT. */ -int cpu_is_ult(void) -{ - static int ult = -1; - - if (ult < 0) { - u32 fm = cpu_family_model(); - if (fm == BROADWELL_FAMILY_ULT || fm == HASWELL_FAMILY_ULT) - ult = 1; - else - ult = 0; - } - - return ult; -} - /* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly * when a core is woken up. */ |