soc/intel/broadwell: Separate PCH in devicetree

Flesh out the PCH configuration into a separate chip. Keep it within the
Broadwell SoC directory for now, to ease moving files around. The boards
were prepared beforehand and the devicetrees require next to no changes.

Tested on out-of-tree Acer Aspire E5-573, still boots.

Change-Id: I28d948f3e6d85e669d12b29516d867c1d1ae9e1a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46700
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 2 insertions, 70 deletions

diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h
index 45d512ac02..81c9780776 100644
--- a/src/soc/intel/broadwell/chip.h
+++ b/src/soc/intel/broadwell/chip.h
@@ -7,70 +7,6 @@
 #include <stdint.h>
 
 struct soc_intel_broadwell_config {
-	/* GPE configuration */
-	uint32_t gpe0_en_1;
-	uint32_t gpe0_en_2;
-	uint32_t gpe0_en_3;
-	uint32_t gpe0_en_4;
-
-	/* GPIO SMI configuration */
-	uint32_t alt_gp_smi_en;
-
-	/* IDE configuration */
-	uint8_t sata_port_map;
-	uint32_t sata_port0_gen3_tx;
-	uint32_t sata_port1_gen3_tx;
-	uint32_t sata_port2_gen3_tx;
-	uint32_t sata_port3_gen3_tx;
-	uint32_t sata_port0_gen3_dtle;
-	uint32_t sata_port1_gen3_dtle;
-	uint32_t sata_port2_gen3_dtle;
-	uint32_t sata_port3_gen3_dtle;
-
-	/*
-	 * SATA DEVSLP Mux
-	 * 0 = port 0 DEVSLP on DEVSLP0/GPIO33
-	 * 1 = port 3 DEVSLP on DEVSLP0/GPIO33
-	 */
-	uint8_t sata_devslp_mux;
-
-	/*
-	 * DEVSLP Disable
-	 * 0: DEVSLP is enabled
-	 * 1: DEVSLP is disabled
-	 */
-	uint8_t sata_devslp_disable;
-
-	/* Generic IO decode ranges */
-	uint32_t gen1_dec;
-	uint32_t gen2_dec;
-	uint32_t gen3_dec;
-	uint32_t gen4_dec;
-
-	/* Enable linear PCIe Root Port function numbers starting at zero */
-	uint8_t pcie_port_coalesce;
-
-	/* Force root port ASPM configuration with port bitmap */
-	uint8_t pcie_port_force_aspm;
-
-	/* Put SerialIO devices into ACPI mode instead of a PCI device */
-	uint8_t sio_acpi_mode;
-
-	/* I2C voltage select: 0=3.3V 1=1.8V */
-	uint8_t sio_i2c0_voltage;
-	uint8_t sio_i2c1_voltage;
-
-	/* Enable ADSP power gating features */
-	uint8_t adsp_d3_pg_enable;
-	uint8_t adsp_sram_pg_enable;
-
-	/*
-	 * Clock Disable Map:
-	 * [21:16] = CLKOUT_PCIE# 5-0
-	 *    [24] = CLKOUT_ITPXDP
-	 */
-	uint32_t icc_clock_disable;
-
 	/*
 	 * Digital Port Hotplug Enable:
 	 *  0x04 = Enabled, 2ms short pulse
@@ -107,9 +43,6 @@ struct soc_intel_broadwell_config {
 
 	struct i915_gpu_controller_info gfx;
 
-	/* Enable S0iX support */
-	int s0ix_enable;
-
 	/*
 	 * Minimum voltage for C6/C7 state:
 	 * 0x67 = 1.6V (full swing)
@@ -132,9 +65,8 @@ struct soc_intel_broadwell_config {
 	/* Enable slow VR ramp rate */
 	int vr_slow_ramp_rate_enable;
 
-	/* Deep SX enable */
-	int deep_sx_enable_ac;
-	int deep_sx_enable_dc;
+	/* Enable S0iX support */
+	int s0ix_enable;
 
 	/* TCC activation offset */
 	uint32_t tcc_offset;