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| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2019-01-30 18:53:14 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-31 08:44:17 +0000 |
| commit | c6c4d00182fe5083a3be43a76aa7bba71f57b0bb (patch) | |
| tree | f000862c87c87f322bc48a3c9a4962d2e96336af /src/soc/intel/broadwell/chip.c | |
| parent | 003fdcbda2fd1559b15e68ea1c5c23be8646ff2c (diff) | |
soc/intel/cannonlake: Make correct C-state entries for S0ix and non-S0ix
TEST=Dump SSDT entries to verify _CST between S0ix enable and disable.
Change-Id: I25e8f8c13bb91c2645e8e9fdfdf9ba4d7022f1b1
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/soc/intel/broadwell/chip.c')
0 files changed, 0 insertions, 0 deletions