broadwell: add new intel SOC

broadwell: Import files from haswell/lynxpoint into soc/broadwell
Reviewed-on: https://chromium-review.googlesource.com/198425
(cherry picked from commit 178400e5709d676dd41e6a75df06faa829e0e3af)

broadwell: Unify and clean up license
Reviewed-on: https://chromium-review.googlesource.com/198426
(cherry picked from commit 30d3c25a0abc76be68477c39a654b95a5975f55d)

broadwell: pch.h: split PM into new header
Reviewed-on: https://chromium-review.googlesource.com/198427
(cherry picked from commit 97a8d0b051f476d0edc06301f57326a718df1373)

broadwell: pch.h: split RCBA into new header
Reviewed-on: https://chromium-review.googlesource.com/198428
(cherry picked from commit fa217361b28fdb8d3a3e85f070dfaf13c0d48135)

broadwell: pch.h: split SATA into new header
Reviewed-on: https://chromium-review.googlesource.com/198429
(cherry picked from commit bf8795ca92f9f0467e7869c701038abb4529ac71)

broadwell: pch.h: split SPI into new header
Reviewed-on: https://chromium-review.googlesource.com/198550
(cherry picked from commit 099af14676a2654ca3e24e66d7b9f0b4ab13cd14)

broadwell: pch.h: split SerialIO into new header
Reviewed-on: https://chromium-review.googlesource.com/198551
(cherry picked from commit 4f3c028686aed78fb07b8792dcf46aebd2268ea6)

broadwell: pch.h: split LPC into new header
Reviewed-on: https://chromium-review.googlesource.com/198552
(cherry picked from commit 10bad5bbb6739c0277fd5330d26a89d60fd5c102)

broadwell: pch.h: split GPIO into new header and clean up
Reviewed-on: https://chromium-review.googlesource.com/198553
(cherry picked from commit 9c97532460562215b78e10b011a29e092a07f3e5)

broadwell: pch.h: split USB into new headers
Reviewed-on: https://chromium-review.googlesource.com/198554
(cherry picked from commit 86ef1a45a2e5f307467b3be48e377569f37b3068)

broadwell: Split IOBP into separate files
Reviewed-on: https://chromium-review.googlesource.com/198734
(cherry picked from commit f93b8bda71728f1383937ad675d2d5fb5a927600)

broadwell: smbus: Extract common code and split header
Reviewed-on: https://chromium-review.googlesource.com/198735
(cherry picked from commit 8052030a9d6b22e8a19938fa9b93e90d08f0057d)

broadwell: Create iomap.h header with platform base addresses
Reviewed-on: https://chromium-review.googlesource.com/198736
(cherry picked from commit b35947d070b28871637dfe2b930a9f2be80958ee)

broadwell: Add header for platform PCI devices
Reviewed-on: https://chromium-review.googlesource.com/198737
(cherry picked from commit 6ac4e56db6e489bb9eaf91a0c3c543399f691500)

broadwell: Split SMM related defines/prototypes to new header
Reviewed-on: https://chromium-review.googlesource.com/198738
(cherry picked from commit 2a2595067077cd918bfd48cad79a684b8e1ff0f4)

broadwell: cpu.h: Split MSR defines to separate header
Reviewed-on: https://chromium-review.googlesource.com/198739
(cherry picked from commit 01148cd2c9edd97cd0c8ef3cfed58bc8c33eb805)

broadwell: Create romstage header file
Reviewed-on: https://chromium-review.googlesource.com/198740
(cherry picked from commit 31c91e811b9e07e7bcba6b9f8f5720a31322eb21)

broadwell: Create ram stage header file
Reviewed-on: https://chromium-review.googlesource.com/198741
(cherry picked from commit 93dde85f98d43d4a1886b59004d1bab4924ad621)

broadwell: Add reference code data interface
Reviewed-on: https://chromium-review.googlesource.com/198743
(cherry picked from commit 9059b8e2308892a48c838c3099404c9cf450df95)

broadwell: Clean up ACPI NVS region
Reviewed-on: https://chromium-review.googlesource.com/198897
(cherry picked from commit d83cc82c36661556eb1e2e437b7ac51d5b8e4a14)

broadwell: Move CTDP ACPI methods to new file
Reviewed-on: https://chromium-review.googlesource.com/198898
(cherry picked from commit fc1e711290df304d18c558d697eea8a5e57061b2)

broadwell: Split EHCI and XHCI ACPI devices
Reviewed-on: https://chromium-review.googlesource.com/198899
(cherry picked from commit 26f437b27e00dbd5c92ea22e76404633a62fb7ca)

broadwell: ACPI: Clean up SerialIO ACPI code
Reviewed-on: https://chromium-review.googlesource.com/198910
(cherry picked from commit ea3cd39566c1bb2ead463a6253b6204a62545d35)

broadwell: ACPI: Remove special handling of LPT-LP chipset
Reviewed-on: https://chromium-review.googlesource.com/198911
(cherry picked from commit 2c54df159bf6759c8f866628e83541de6f4e28f6)

broadwell: ACPI: Clean up use of base address defines
Reviewed-on: https://chromium-review.googlesource.com/198912
(cherry picked from commit 34e4788955bceff01631fd0b4dbf0aa24cf56b75)

broadwell: ACPI: Clean up and fix formatting
Reviewed-on: https://chromium-review.googlesource.com/198913
(cherry picked from commit bc0f7c6d2f95681eb987bb6ff6baf2d16cc77050)

broadwell: Add header for ACPI defines and prototypes
Reviewed-on: https://chromium-review.googlesource.com/198914
(cherry picked from commit 9951e7931942d2921f92f6e094b1cc32c190eab9)

broadwell: Add reset_system function and header
Reviewed-on: https://chromium-review.googlesource.com/198915
(cherry picked from commit 6d1efb94bd39bcd6f7e3e0de2f3299a384b109ef)

broadwell: Move PCODE MMIO defines to systemagent.h
Reviewed-on: https://chromium-review.googlesource.com/198916
(cherry picked from commit abb5f87e548fbde3a08e14a18714b4e4391c955f)

broadwell: Unify chip.h and add chip.c
Reviewed-on: https://chromium-review.googlesource.com/198917
(cherry picked from commit a9c2d7ff3afa1e2a10be85ccc72b7db0f2aaafe1)

broadwell: Rename HASWELL_BCLK to CPU_BCLK
Reviewed-on: https://chromium-review.googlesource.com/198918
(cherry picked from commit 65ac1a07abaf14eb42fec6c5df67d2d3688ad5a1)

broadwell: Clean up broadwell/cpu.h
Reviewed-on: https://chromium-review.googlesource.com/198919
(cherry picked from commit 17353803babc8ace279e105c012130678226144e)

broadwell: Clean up broadwell/systemagent.h
Reviewed-on: https://chromium-review.googlesource.com/198920
(cherry picked from commit 49d7a023f3ff04a65d16622aa9b2fa6004b693ae)

broadwell: Clean up broadwell/pch.h
Reviewed-on: https://chromium-review.googlesource.com/198921
(cherry picked from commit 17da652b4408a91fcfea99dd35fe9f9e1bdcf03b)

broadwell: Clean up management engine driver
Reviewed-on: https://chromium-review.googlesource.com/198922
(cherry picked from commit 4fce5fbb56dc4f31b77e5ada05463c043ad5be72)

broadwell: Add common CPUID and PCI Device ID defines
Reviewed-on: https://chromium-review.googlesource.com/198923
(cherry picked from commit c6bf20309f33168ea2cc4634cbda5ec242824ba8)

broadwell: Clean up and expand report_platform
Reviewed-on: https://chromium-review.googlesource.com/198924
(cherry picked from commit 5082d4824db149e867a2cd8be34c932b03754022)

broadwell: Clean up the bootblock code
Reviewed-on: https://chromium-review.googlesource.com/198925
(cherry picked from commit ba0206ab76fe0b6834a14dc57f400d139094623c)

broadwell: Clean up ramstage device and driver operations
Reviewed-on: https://chromium-review.googlesource.com/199180
(cherry picked from commit d8fc9daf129738713a5059286b7ead004f3b7569)

broadwell: Clean up XHCI and EHCI ramstage drivers
Reviewed-on: https://chromium-review.googlesource.com/199181
(cherry picked from commit d355247333a828a146ce7cf9b92a63da74119c1d)

broadwell: Clean up gpio handling code
Reviewed-on: https://chromium-review.googlesource.com/199182
(cherry picked from commit d62cef1970fe75f8166315016b3d8415cddcab20)

broadwell: Clean up the PCH generic code
Reviewed-on: https://chromium-review.googlesource.com/199183
(cherry picked from commit 3b93b3ea79965d5ac831bf9015e49330f157b0ff)

broadwell: Move get_top_of_ram() and cbmem_top() to memmap.c
Reviewed-on: https://chromium-review.googlesource.com/199184
(cherry picked from commit 68955ba4ff8b49ff466d7badaa934bd143026ba7)

broadwell: Clean up pmutil.c
Reviewed-on: https://chromium-review.googlesource.com/199185
(cherry picked from commit b6fb672ae879e17422f7449f70c3669055096f84)

broadwell: pmutil: Add new acpi_sci_irq() function
Reviewed-on: https://chromium-review.googlesource.com/199186
(cherry picked from commit 80ad8bb9bdc75f180e667861fed42a3844226bc5)

broadwell: Clean up HDA ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199187
(cherry picked from commit b4962acd706eaa66c1c3ef4d22eba313642fbb2d)

broadwell: Clean up cache_as_ram assembly
Reviewed-on: https://chromium-review.googlesource.com/199188
(cherry picked from commit 8a457b82610b604ae7f69e2500815ce411c2d02d)

broadwell: romstage: Separate stack helper functions
Reviewed-on: https://chromium-review.googlesource.com/199189
(cherry picked from commit c220383c90466fc2dbf4b6107679b08ecb4aadad)

broadwell: Add function to read WPSR from SPI
Reviewed-on: https://chromium-review.googlesource.com/199190
(cherry picked from commit 935404da1157d606b913eff6c2635ae898e9980a)

broadwell: Clean up SMBUS code in romstage and ramstage
Reviewed-on: https://chromium-review.googlesource.com/199191
(cherry picked from commit 6ae9d93c1a6f14da6429a4e5b01619c9ccaefdaa)

broadwell: SPI: Clean up romstage and ramstage code
Reviewed-on: https://chromium-review.googlesource.com/199192
(cherry picked from commit 28ffd71a416aee2ab54bc5d782cfeef31d4d30bf)

broadwell: Clean up PCIe root port ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199193
(cherry picked from commit 781f3a1b72c72f0bb05f5524edec471ad13ec90e)

broadwell: Clean up minihd ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199194
(cherry picked from commit a52d275e41fdcbf9895d07350725609d9be1ff0e)

broadwell: Update romstage main to follow baytrail format
Reviewed-on: https://chromium-review.googlesource.com/199361
(cherry picked from commit 0678c739af84c871922ffba5594132b25e471ddd)

broadwell: Add CPU set_max_freq function for romstage
Reviewed-on: https://chromium-review.googlesource.com/199362
(cherry picked from commit 68b0122472af27f38502d42a8a6c80678ddbbba6)

broadwell: romstage: Add chipset_power_state implementation
Reviewed-on: https://chromium-review.googlesource.com/199363
(cherry picked from commit 761cec3b6bb9bde579c3214f3f1196f65700757c)

broadwell: romstage: Convert systemagent init to reg_script
Reviewed-on: https://chromium-review.googlesource.com/199364
(cherry picked from commit c2ea2d3a0c7555a353fb9a1d4a63e773ac8961b2)

broadwell: romstage: Convert pch init to reg_script
Reviewed-on: https://chromium-review.googlesource.com/199365
(cherry picked from commit 4383de5846e97ca5aee6dd210459d8dba0af981c)

broadwell: elog: Use chipset_power_state for events
Reviewed-on: https://chromium-review.googlesource.com/199366
(cherry picked from commit 0ef5961ebe3a7037d5fbe361fbc70a87ac2edad9)

broadwell: Clean up SATA ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199367
(cherry picked from commit ffa5743f74551bd48aa7e5445ce7cd9dc7b07ce8)

broadwell: Update ramstage graphics driver to support broadwell
Reviewed-on: https://chromium-review.googlesource.com/199368
(cherry picked from commit bb01deb8bbed56f15e1143504e4cf012ecf5a281)

broadwell: Update raminit to follow baytrail layout
Reviewed-on: https://chromium-review.googlesource.com/199369
(cherry picked from commit 3f25c23dc58f85d2521916cd6edbe9deeeb8d523)

broadwell: Update and unify the finalize steps
Reviewed-on: https://chromium-review.googlesource.com/199390
(cherry picked from commit ddc4c116b42d38dfdfc45ef4388fbfab32ca48fa)

broadwell: Clean up SMM code
Reviewed-on: https://chromium-review.googlesource.com/199391
(cherry picked from commit 8295e56c9b643fd4b9267d70b5efd0cf94dd67dd)

broadwell: Clean up LPC ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199392
(cherry picked from commit 28326aeaaf304c9262866588d91b79b37d1d9a2e)

broadwell: Clean up systemagent ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199393
(cherry picked from commit 749988fff07eab8d2c9ebc731e3ed9e427b3f7b3)

broadwell: Move C-state configuration information to acpi.c
Reviewed-on: https://chromium-review.googlesource.com/199394
(cherry picked from commit 198a3cd5cbd009be406298cbb53163f075fe9990)

broadwell: Clean up CPU ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199395
(cherry picked from commit 8159689bba479bab6fd2e949e3e1c3f817088969)

broadwell: Do not reserve SMM relocation region
Reviewed-on: https://chromium-review.googlesource.com/199402
(cherry picked from commit e2ab52340e3d3a97a3f8dbdad8fac9f7769d1b4c)

broadwell: Add an early ramstage driver
Reviewed-on: https://chromium-review.googlesource.com/199403
(cherry picked from commit c7a8c867101b49a7f9f17ec1a8777a8db145f3e3)

broadwell: Support for second reference code binary
Reviewed-on: https://chromium-review.googlesource.com/199404
(cherry picked from commit abb99b36e97c4f739b23abed6146fea370bbbec2)

broadwell: Clean up serialio init code
Reviewed-on: https://chromium-review.googlesource.com/199405
(cherry picked from commit e09a1f8520a7b72451a1e2068b200f7c5451f489)

broadwell: acpi: Add function to fill out FADT
Reviewed-on: https://chromium-review.googlesource.com/199406
(cherry picked from commit 7e58f43e46d4382cf4541057f81fe6be3e4d6e74)

broadwell: Update C-state table creation
Reviewed-on: https://chromium-review.googlesource.com/199407
(cherry picked from commit 68b1f70e32e1d0c6fc4332dce402ad78334e0063)

broadwell: acpi: Clean up acpi table creation code
Reviewed-on: https://chromium-review.googlesource.com/199408
(cherry picked from commit 49088b312b159bb17a9330eda6a88d6f324ea146)

broadwell: acpi: Add ACPI table create helper functions
Reviewed-on: https://chromium-review.googlesource.com/199409
(cherry picked from commit 344c3c511d0341457525ef4d6eb70201404fc62c)

broadwell: Add soc/intel/broadwell Makefiles
Reviewed-on: https://chromium-review.googlesource.com/199410
(cherry picked from commit ea8f97738eadd3b0b6a642754df7a7d22e547ffc)

broadwell: Add Kconfig for broadwell soc
Reviewed-on: https://chromium-review.googlesource.com/199411
(cherry picked from commit 8c99038a5c20812497619134c66d45bc4f21c8fe)

Squashed 78 commits for broadwell that form a solid code base.

Change-Id: I365ca9a45978b5e0cc5237f884e20a44f62a0e63
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6964
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

5 files changed, 289 insertions, 0 deletions

diff --git a/src/soc/intel/broadwell/bootblock/Makefile.inc b/src/soc/intel/broadwell/bootblock/Makefile.inc
new file mode 100644
index 0000000000..2ca5a4569f
--- /dev/null
+++ b/src/soc/intel/broadwell/bootblock/Makefile.inc
@@ -0,0 +1 @@
+chipset_bootblock_inc += $(src)/soc/intel/broadwell/bootblock/timestamp.inc
diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/bootblock/cpu.c
new file mode 100644
index 0000000000..11f1833fd0
--- /dev/null
+++ b/src/soc/intel/broadwell/bootblock/cpu.c
@@ -0,0 +1,131 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <arch/io.h>
+#include <cpu/intel/microcode/microcode.c>
+#include <broadwell/rcba.h>
+#include <broadwell/msr.h>
+
+static void set_var_mtrr(
+	unsigned reg, unsigned base, unsigned size, unsigned type)
+
+{
+	/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
+	msr_t basem, maskm;
+	basem.lo = base | type;
+	basem.hi = 0;
+	wrmsr(MTRRphysBase_MSR(reg), basem);
+	maskm.lo = ~(size - 1) | MTRRphysMaskValid;
+	maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
+	wrmsr(MTRRphysMask_MSR(reg), maskm);
+}
+
+static void enable_rom_caching(void)
+{
+	msr_t msr;
+
+	disable_cache();
+	/* Why only top 4MiB ? */
+	set_var_mtrr(1, CACHE_ROM_BASE, CONFIG_CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
+	enable_cache();
+
+	/* Enable Variable MTRRs */
+	msr.hi = 0x00000000;
+	msr.lo = 0x00000800;
+	wrmsr(MTRRdefType_MSR, msr);
+}
+
+static void set_flex_ratio_to_tdp_nominal(void)
+{
+	msr_t flex_ratio, msr;
+	u32 soft_reset;
+	u8 nominal_ratio;
+
+	/* Check for Flex Ratio support */
+	flex_ratio = rdmsr(MSR_FLEX_RATIO);
+	if (!(flex_ratio.lo & FLEX_RATIO_EN))
+		return;
+
+	/* Check for >0 configurable TDPs */
+	msr = rdmsr(MSR_PLATFORM_INFO);
+	if (((msr.hi >> 1) & 3) == 0)
+		return;
+
+	/* Use nominal TDP ratio for flex ratio */
+	msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
+	nominal_ratio = msr.lo & 0xff;
+
+	/* See if flex ratio is already set to nominal TDP ratio */
+	if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
+		return;
+
+	/* Set flex ratio to nominal TDP ratio */
+	flex_ratio.lo &= ~0xff00;
+	flex_ratio.lo |= nominal_ratio << 8;
+	flex_ratio.lo |= FLEX_RATIO_LOCK;
+	wrmsr(MSR_FLEX_RATIO, flex_ratio);
+
+	/* Set flex ratio in soft reset data register bits 11:6.
+	 * RCBA region is enabled in southbridge bootblock */
+	soft_reset = RCBA32(SOFT_RESET_DATA);
+	soft_reset &= ~(0x3f << 6);
+	soft_reset |= (nominal_ratio & 0x3f) << 6;
+	RCBA32(SOFT_RESET_DATA) = soft_reset;
+
+	/* Set soft reset control to use register value */
+	RCBA32_OR(SOFT_RESET_CTRL, 1);
+
+	/* Issue warm reset, will be "CPU only" due to soft reset data */
+	outb(0x0, 0xcf9);
+	outb(0x6, 0xcf9);
+	while (1) {
+		asm("hlt");
+	}
+}
+
+static void check_for_clean_reset(void)
+{
+	msr_t msr;
+	msr = rdmsr(MTRRdefType_MSR);
+
+	/* Use the MTRR default type MSR as a proxy for detecting INIT#.
+	 * Reset the system if any known bits are set in that MSR. That is
+	 * an indication of the CPU not being properly reset. */
+	if (msr.lo & (MTRRdefTypeEn | MTRRdefTypeFixEn)) {
+		outb(0x0, 0xcf9);
+		outb(0x6, 0xcf9);
+		while (1) {
+			asm("hlt");
+		}
+	}
+}
+
+static void bootblock_cpu_init(void)
+{
+	/* Set flex ratio and reset if needed */
+	set_flex_ratio_to_tdp_nominal();
+	check_for_clean_reset();
+	enable_rom_caching();
+	intel_update_microcode_from_cbfs();
+}
diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/bootblock/pch.c
new file mode 100644
index 0000000000..9e76f7976f
--- /dev/null
+++ b/src/soc/intel/broadwell/bootblock/pch.c
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <cpu/x86/tsc.h>
+#include <broadwell/iomap.h>
+#include <broadwell/lpc.h>
+#include <broadwell/pci_devs.h>
+#include <broadwell/rcba.h>
+#include <broadwell/spi.h>
+
+static void store_initial_timestamp(void)
+{
+	/* Two 32bit scratchpad registers available:
+	 * D0:F0  0xdc (SKPAD)
+	 * D31:F2 0xd0 (SATA SP)
+	 */
+	tsc_t tsc = rdtsc();
+	pci_write_config32(SA_DEV_ROOT, 0xdc, tsc.lo);
+	pci_write_config32(PCH_DEV_SATA, 0xd0, tsc.hi);
+}
+
+/*
+ * Enable Prefetching and Caching.
+ */
+static void enable_spi_prefetch(void)
+{
+	u8 reg8 = pci_read_config8(PCH_DEV_LPC, 0xdc);
+	reg8 &= ~(3 << 2);
+	reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+	pci_write_config8(PCH_DEV_LPC, 0xdc, reg8);
+}
+
+
+static void map_rcba(void)
+{
+	pci_write_config32(PCH_DEV_LPC, RCBA, RCBA_BASE_ADDRESS | 1);
+}
+
+static void enable_port80_on_lpc(void)
+{
+	/* Enable port 80 POST on LPC. The chipset does this by deafult,
+	 * but it doesn't appear to hurt anything. */
+	u32 gcs = RCBA32(GCS);
+	gcs = gcs & ~0x4;
+	RCBA32(GCS) = gcs;
+}
+
+static void set_spi_speed(void)
+{
+	u32 fdod;
+	u8 ssfc;
+
+	/* Observe SPI Descriptor Component Section 0 */
+	SPIBAR32(SPIBAR_FDOC) = 0x1000;
+
+	/* Extract the Write/Erase SPI Frequency from descriptor */
+	fdod = SPIBAR32(SPIBAR_FDOD);
+	fdod >>= 24;
+	fdod &= 7;
+
+	/* Set Software Sequence frequency to match */
+	ssfc = SPIBAR8(SPIBAR_SSFC + 2);
+	ssfc &= ~7;
+	ssfc |= fdod;
+	SPIBAR8(SPIBAR_SSFC + 2) = ssfc;
+}
+
+static void bootblock_southbridge_init(void)
+{
+#if CONFIG_COLLECT_TIMESTAMPS
+	store_initial_timestamp();
+#endif
+	map_rcba();
+	enable_spi_prefetch();
+	enable_port80_on_lpc();
+	set_spi_speed();
+}
diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/soc/intel/broadwell/bootblock/systemagent.c
new file mode 100644
index 0000000000..b2dd27b1a1
--- /dev/null
+++ b/src/soc/intel/broadwell/bootblock/systemagent.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <broadwell/pci_devs.h>
+#include <broadwell/systemagent.h>
+
+static void bootblock_northbridge_init(void)
+{
+	uint32_t reg;
+
+	/*
+	 * The "io" variant of the config access is explicitly used to
+	 * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to
+	 * to true. That way all subsequent non-explicit config accesses use
+	 * MCFG. This code also assumes that bootblock_northbridge_init() is
+	 * the first thing called in the non-asm boot block code. The final
+	 * assumption is that no assembly code is using the
+	 * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses.
+	 *
+	 * The PCIEXBAR is assumed to live in the memory mapped IO space under
+	 * 4GiB.
+	 */
+	reg = 0;
+	pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg);
+	reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
+	pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg);
+}
diff --git a/src/soc/intel/broadwell/bootblock/timestamp.inc b/src/soc/intel/broadwell/bootblock/timestamp.inc
new file mode 100644
index 0000000000..f565775ed8
--- /dev/null
+++ b/src/soc/intel/broadwell/bootblock/timestamp.inc
@@ -0,0 +1,19 @@
+/* Store the initial timestamp for booting in mmx registers. This works
+ * because the bootblock isn't being compiled with MMX support so mm0 and
+ * mm1 will be preserved into romstage. */
+	.code32
+
+.global stash_timestamp
+stash_timestamp:
+
+	/* Save the BIST value */
+	movl	%eax, %ebp
+
+	finit
+	rdtsc
+	movd	%eax, %mm0
+	movd	%edx, %mm1
+
+	/* Restore the BIST value to %eax */
+	movl	%ebp, %eax
+