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authorMarc Jones <marc.jones@se-eng.com>2014-12-26 22:11:14 -0700
committerMarc Jones <marc.jones@se-eng.com>2014-12-31 21:22:24 +0100
commita6354a1acadc7825364c6a6e7fd3b24a405a62a1 (patch)
treec947844cc6568280240c8bdc225fa581b1ea23af /src/soc/intel/broadwell/bootblock
parentdffd892e47bb8bbfb920447275a2d6b00be904ce (diff)
broadwell: Preparations for building
Updated Intel Broadwell for differences in the source based on the chromium tree. It is missing most of the recent updates on coreboot.org. - makefile changes for Elog and IDF tool - kconfig changes for ME, ucode, and other updates - update oprom flag - update timestamp mechanism - cbfs payload function is now generic Change-Id: I82bd0792e9dcf81085246873164de6600528d6fe Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7939 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
Diffstat (limited to 'src/soc/intel/broadwell/bootblock')
-rw-r--r--src/soc/intel/broadwell/bootblock/cpu.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/bootblock/cpu.c
index da7b99df62..e20ced2cf6 100644
--- a/src/soc/intel/broadwell/bootblock/cpu.c
+++ b/src/soc/intel/broadwell/bootblock/cpu.c
@@ -48,7 +48,7 @@ static void enable_rom_caching(void)
disable_cache();
/* Why only top 4MiB ? */
- set_var_mtrr(1, CACHE_ROM_BASE, CONFIG_CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
+ set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
enable_cache();
/* Enable Variable MTRRs */