diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2018-12-22 16:59:44 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-15 17:57:33 +0000 |
commit | e43972474c0eebc478722f7c371a8c68318f24cf (patch) | |
tree | 34abf5f2a18cb350fe4871b4e8509c5da4705d37 /src/soc/intel/broadwell/bootblock | |
parent | 4d56a0625516ba436903d59d9c0a4a13827d89be (diff) |
soc/intel/broadwell: Enable LPC/SIO setup in bootblock
This allows for serial console during the bootblock and enables
bootblock console by default.
Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/soc/intel/broadwell/bootblock')
-rw-r--r-- | src/soc/intel/broadwell/bootblock/pch.c | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/bootblock/pch.c index 1301610947..590961b361 100644 --- a/src/soc/intel/broadwell/bootblock/pch.c +++ b/src/soc/intel/broadwell/bootblock/pch.c @@ -19,6 +19,9 @@ #include <soc/pci_devs.h> #include <soc/rcba.h> #include <soc/spi.h> +#include <reg_script.h> +#include <soc/pm.h> +#include <soc/romstage.h> #include <cpu/intel/car/bootblock.h> /* @@ -67,10 +70,56 @@ static void set_spi_speed(void) SPIBAR8(SPIBAR_SSFC + 2) = ssfc; } +const struct reg_script pch_early_init_script[] = { + /* Setup southbridge BARs */ + REG_PCI_WRITE32(RCBA, RCBA_BASE_ADDRESS | 1), + REG_PCI_WRITE32(PMBASE, ACPI_BASE_ADDRESS | 1), + REG_PCI_WRITE8(ACPI_CNTL, ACPI_EN), + REG_PCI_WRITE32(GPIO_BASE, GPIO_BASE_ADDRESS | 1), + REG_PCI_WRITE8(GPIO_CNTL, GPIO_EN), + + /* Set COM1/COM2 decode range */ + REG_PCI_WRITE16(LPC_IO_DEC, 0x0010), + /* Enable legacy decode ranges */ + REG_PCI_WRITE16(LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN | + COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN), + + /* Enable IOAPIC */ + REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + OIC, 0x0100), + /* Read back for posted write */ + REG_MMIO_READ16(RCBA_BASE_ADDRESS + OIC), + + /* Set HPET address and enable it */ + REG_MMIO_RMW32(RCBA_BASE_ADDRESS + HPTC, ~3, (1 << 7)), + /* Read back for posted write */ + REG_MMIO_READ32(RCBA_BASE_ADDRESS + HPTC), + /* Enable HPET to start counter */ + REG_MMIO_OR32(HPET_BASE_ADDRESS + 0x10, (1 << 0)), + + /* Disable reset */ + REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 5)), + /* TCO timer halt */ + REG_IO_OR16(ACPI_BASE_ADDRESS + TCO1_CNT, TCO_TMR_HLT), + + /* Enable upper 128 bytes of CMOS */ + REG_MMIO_OR32(RCBA_BASE_ADDRESS + RC, (1 << 2)), + + /* Disable unused device (always) */ + REG_MMIO_OR32(RCBA_BASE_ADDRESS + FD, PCH_DISABLE_ALWAYS), + + REG_SCRIPT_END +}; + +static void pch_early_lpc(void) +{ + reg_script_run_on_dev(PCH_DEV_LPC, pch_early_init_script); +} + void bootblock_early_southbridge_init(void) { map_rcba(); enable_spi_prefetch(); enable_port80_on_lpc(); set_spi_speed(); + pch_early_lpc(); } |