diff options
| author | Kevin Paul Herbert <kph@meraki.net> | 2014-12-24 18:43:20 -0800 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-02-15 08:50:22 +0100 |
| commit | bde6d309dfafe58732ec46314a2d4c08974b62d4 (patch) | |
| tree | 17ba00565487ddfbb5759c96adfbb3fffe2a4550 /src/soc/intel/broadwell/adsp.c | |
| parent | 4b10dec1a66122b515b2191f823d7fd379ec655f (diff) | |
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.
Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/broadwell/adsp.c')
| -rw-r--r-- | src/soc/intel/broadwell/adsp.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c index 2a6dc1744a..41372158a0 100644 --- a/src/soc/intel/broadwell/adsp.c +++ b/src/soc/intel/broadwell/adsp.c @@ -58,7 +58,8 @@ static void adsp_init(struct device *dev) * SNOOP_REQ[13]=1b SNOOP_SCALE[12:10]=100b (1ms) SNOOP_VAL[9:0]=3h */ tmp32 = pch_is_wpt() ? ADSP_SHIM_BASE_WPT : ADSP_SHIM_BASE_LPT; - write32(bar0->base + tmp32 + ADSP_SHIM_LTRC, ADSP_SHIM_LTRC_VALUE); + write32(res2mmio(bar0, tmp32 + ADSP_SHIM_LTRC, 0), + ADSP_SHIM_LTRC_VALUE); /* Program VDRTCTL2 D19:F0:A8[31:0] = 0x00000fff */ pci_write_config32(dev, ADSP_PCI_VDRTCTL2, ADSP_VDRTCTL2_VALUE); @@ -115,9 +116,9 @@ static void adsp_init(struct device *dev) ADSP_PCICFGCTL_ACPIIE); /* Put ADSP in D3hot */ - tmp32 = read32(bar1->base + PCH_PCS); + tmp32 = read32(res2mmio(bar1, PCH_PCS, 0)); tmp32 |= PCH_PCS_PS_D3HOT; - write32(bar1->base + PCH_PCS, tmp32); + write32(res2mmio(bar1, PCH_PCS, 0), tmp32); } else { printk(BIOS_INFO, "ADSP: Enable PCI Mode IRQ23\n"); |