broadwell: Misc updates from 2.1.0 ref code

- ADSP IRQ should be exclusive
- HDA should write reg 0x43 even if disabled
- A few clock gating tweaks based on ref code changes
- Move SATA clock gating to sata.c where SIR changes are done
- Add support for enabling Deep SX in AC/DC modes
- CLKREQ VR Idle for enabled PCIE ports

BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus

Original-Change-Id: Icece58e32b7a5d2b359debd5516a230cae3fd48c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211611
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit c0e22ba043ed96bdddca4989b2f29d0e989f6fef)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: If5f5e1666aa9660e31305ee6369f2febf6757b99
Reviewed-on: http://review.coreboot.org/8952
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>

1 files changed, 12 insertions, 2 deletions

diff --git a/src/soc/intel/broadwell/acpi/adsp.asl b/src/soc/intel/broadwell/acpi/adsp.asl
index d50dce6fcd..cb10d9a9ad 100644
--- a/src/soc/intel/broadwell/acpi/adsp.asl
+++ b/src/soc/intel/broadwell/acpi/adsp.asl
@@ -36,12 +36,12 @@ Device (ADSP)
 	{
 		Memory32Fixed (ReadWrite, 0x00000000, 0x00100000, BAR0)
 		Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR1)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {3}
+		Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {3}
 	})
 
 	Method (_CRS, 0, NotSerialized)
 	{
-		// Update BAR0 address and length if set in NVS
+		// Update BAR address and length if set in NVS
 		If (LNotEqual (\S8B0, Zero)) {
 			CreateDwordField (^RBUF, ^BAR0._BAS, B8A0)
 			CreateDwordField (^RBUF, ^BAR1._BAS, B8A1)
@@ -60,4 +60,14 @@ Device (ADSP)
 			Return (0xF)
 		}
 	}
+
+	Device (I2S0)
+	{
+		Name (_ADR, 0)
+	}
+
+	Device (I2S1)
+	{
+		Name (_ADR, 1)
+	}
 }