diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-31 00:33:04 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-02-07 19:31:34 +0000 |
| commit | c715dc80f92f5cf1d29b53f2b2166e2a4f4b3dc4 (patch) | |
| tree | 08dc25d5ae137d824ae0db2f0be90956f521cbdc /src/soc/intel/broadwell/acpi | |
| parent | 84a37b9d55e8da6137bfeb9d2e866ae4273983a8 (diff) | |
soc/intel/broadwell: Use common {DMI,EP,MCH}BAR accessors
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I04dbeade44d480301c9f7d336449bc54e56cb7bc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50169
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/broadwell/acpi')
| -rw-r--r-- | src/soc/intel/broadwell/acpi/ctdp.asl | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/acpi/hostbridge.asl | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/broadwell/acpi/ctdp.asl b/src/soc/intel/broadwell/acpi/ctdp.asl index b18ec78ecd..67ceb82ad8 100644 --- a/src/soc/intel/broadwell/acpi/ctdp.asl +++ b/src/soc/intel/broadwell/acpi/ctdp.asl @@ -9,7 +9,7 @@ Scope (\_SB.PCI0.MCHC) Name (CTCU, 2) /* CTDP Up Select */ Name (SPL1, 0) /* Saved PL1 value */ - OperationRegion (MCHB, SystemMemory, MCH_BASE_ADDRESS + 0x5000, 0x1000) + OperationRegion (MCHB, SystemMemory, CONFIG_FIXED_MCHBAR_MMIO_BASE + 0x5000, 0x1000) Field (MCHB, DWordAcc, Lock, Preserve) { Offset (0x930), /* PACKAGE_POWER_SKU */ diff --git a/src/soc/intel/broadwell/acpi/hostbridge.asl b/src/soc/intel/broadwell/acpi/hostbridge.asl index 325a736456..e36fa47677 100644 --- a/src/soc/intel/broadwell/acpi/hostbridge.asl +++ b/src/soc/intel/broadwell/acpi/hostbridge.asl @@ -175,9 +175,9 @@ Device (PDRC) Name (PDRS, ResourceTemplate() { Memory32Fixed (ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) - Memory32Fixed (ReadWrite, MCH_BASE_ADDRESS, MCH_BASE_SIZE) - Memory32Fixed (ReadWrite, DMI_BASE_ADDRESS, DMI_BASE_SIZE) - Memory32Fixed (ReadWrite, EP_BASE_ADDRESS, EP_BASE_SIZE) + Memory32Fixed (ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, MCH_BASE_SIZE) + Memory32Fixed (ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, DMI_BASE_SIZE) + Memory32Fixed (ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, EP_BASE_SIZE) Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) Memory32Fixed (ReadWrite, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE) Memory32Fixed (ReadWrite, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE) |