broadwell: ACPI, romstage, and other updates

broadwell: Add romstage usbdebug support
Reviewed-on: https://chromium-review.googlesource.com/199412
(cherry picked from commit 1050e7d3be6ec1e4fe5aa2df408f4bb6d33a42b5)

broadwell: Add romstage code to configure PCH UART for console
Reviewed-on: https://chromium-review.googlesource.com/199807
(cherry picked from commit ecebda4eb5d6fe58473d25c2898ba1a2eac0f39a)

broadwell: Expand the PCI device convenience macros
Reviewed-on: https://chromium-review.googlesource.com/199891
(cherry picked from commit f8c54c70f136cd2cb8f977bc25661974d7e529ad)

broadwell: Add ramstage driver for ADSP
Reviewed-on: https://chromium-review.googlesource.com/199892
(cherry picked from commit e8e986b0ba52bbfc9923d71009fbd31e749ca43f)

broadwell: Update ACPI devices
Reviewed-on: https://chromium-review.googlesource.com/201080
(cherry picked from commit 2446b35578eb36e0009415bec340059135751549)

broadwell: Reserve DPR region
Reviewed-on: https://chromium-review.googlesource.com/201081
(cherry picked from commit 8ecd9d2096db2bded6f27ef6ee9a9b39ce2dfec6)

broadwell: Remove old pei_data and add cpu function for romstage
Reviewed-on: https://chromium-review.googlesource.com/201690
(cherry picked from commit d206c9cdd69519d502a90bb0595f0e3a7cb50274)

broadwell: Fixes for graphics without executing VBIOS
Reviewed-on: https://chromium-review.googlesource.com/202356
(cherry picked from commit 0c031df1ce92c875e95ddfd3f026f649c342c7fa)

broadwell: Fix compilation failure when loglevel is lowered
Reviewed-on: https://chromium-review.googlesource.com/202357
(cherry picked from commit 708ce78b2bfae5664b1238e17b086c88cac55bdc)

broadwell: Disable GPIO controller interrupt
Reviewed-on: https://chromium-review.googlesource.com/203645
(cherry picked from commit 2d17e98eded5958258ba5c0abf600284d8d03af9)

broadwell: Add support for E0 stepping
Reviewed-on: https://chromium-review.googlesource.com/205160
(cherry picked from commit 802e9d371418cc7a7fc7af131d7e5dda0ae5b273)

broadwell: misc updates for CPU driver
Reviewed-on: https://chromium-review.googlesource.com/205161
(cherry picked from commit ea1d403817ee193648f2c119fd45894e32e57e97)

broadwell: Read power state earlier and store in romstage params
Reviewed-on: https://chromium-review.googlesource.com/208151
(cherry picked from commit b2198d71084ad3c1360a0bfedc46c8dd3825bd0e)

broadwell: Add parameters to pei_data structure
Reviewed-on: https://chromium-review.googlesource.com/208153
(cherry picked from commit 423fbf67e497a907fbc8e12caf2929d4951858af)

broadwell: Move platform report output after power state is read
Reviewed-on: https://chromium-review.googlesource.com/208213
(cherry picked from commit acedf4146bf9377133433046dae1fa9c8bc69d78)

Squashed 15 commits for broadwell support.

Change-Id: I87e320d3d5376b84dd9c146b0b833e5ce53244aa
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6982
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

6 files changed, 284 insertions, 30 deletions

diff --git a/src/soc/intel/broadwell/acpi/adsp.asl b/src/soc/intel/broadwell/acpi/adsp.asl
new file mode 100644
index 0000000000..d50dce6fcd
--- /dev/null
+++ b/src/soc/intel/broadwell/acpi/adsp.asl
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Device (ADSP)
+{
+	Method (_HID, 0, Serialized)
+	{
+		If (\ISWP ()) {
+			// WildcatPoint
+			Return ("INT3438")
+		}
+
+		// LynxPoint-LP
+		Return ("INT33C8")
+	}
+	Name (_UID, 1)
+	Name (_DDN, "Intel Smart Sound Technology")
+
+	Name (RBUF, ResourceTemplate ()
+	{
+		Memory32Fixed (ReadWrite, 0x00000000, 0x00100000, BAR0)
+		Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR1)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {3}
+	})
+
+	Method (_CRS, 0, NotSerialized)
+	{
+		// Update BAR0 address and length if set in NVS
+		If (LNotEqual (\S8B0, Zero)) {
+			CreateDwordField (^RBUF, ^BAR0._BAS, B8A0)
+			CreateDwordField (^RBUF, ^BAR1._BAS, B8A1)
+			Store (\S8B0, B8A0)
+			Store (\S8B1, B8A1)
+		}
+
+		Return (RBUF)
+	}
+
+	Method (_STA, 0, NotSerialized)
+	{
+		If (LEqual (\S8EN, 0)) {
+			Return (0x0)
+		} Else {
+			Return (0xF)
+		}
+	}
+}
diff --git a/src/soc/intel/broadwell/acpi/device_nvs.asl b/src/soc/intel/broadwell/acpi/device_nvs.asl
index d5af2e8cc9..1d2aa78edb 100644
--- a/src/soc/intel/broadwell/acpi/device_nvs.asl
+++ b/src/soc/intel/broadwell/acpi/device_nvs.asl
@@ -27,6 +27,7 @@ S4EN,	8,	// SPI1 Enable
 S5EN,	8,	// UART0 Enable
 S6EN,	8,	// UART1 Enable
 S7EN,	8,	// SDIO Enable
+S8EN,	8,	// ADSP Enable
 
 /* BAR 0 */
 
@@ -38,6 +39,7 @@ S4B0,	32,	// SPI1 BAR0
 S5B0,	32,	// UART0 BAR0
 S6B0,	32,	// UART1 BAR0
 S7B0,	32,	// SDIO BAR0
+S8B0,	32,	// ADSP BAR0
 
 /* BAR 1 */
 
@@ -49,3 +51,4 @@ S4B1,	32,	// SPI1 BAR1
 S5B1,	32,	// UART0 BAR1
 S6B1,	32,	// UART1 BAR1
 S7B1,	32,	// SDIO BAR1
+S8B1,	32,	// ADSP BAR1
diff --git a/src/soc/intel/broadwell/acpi/gpio.asl b/src/soc/intel/broadwell/acpi/gpio.asl
index 5df512e0e3..c6d8753975 100644
--- a/src/soc/intel/broadwell/acpi/gpio.asl
+++ b/src/soc/intel/broadwell/acpi/gpio.asl
@@ -20,8 +20,16 @@
 Device (GPIO)
 {
 	// GPIO Controller
-	Name (_HID, "INT33C7")
-	Name (_CID, "INT33C7")
+	Method (_HID)
+	{
+		If (\ISWP ()) {
+			// WildcatPoint
+			Return ("INT3437")
+		}
+
+		// LynxPoint-LP
+		Return ("INT33C7")
+	}
 	Name (_UID, 1)
 
 	Name (RBUF, ResourceTemplate()
@@ -39,8 +47,9 @@ Device (GPIO)
 			,            // ResourceSourceIndex
 			,            // ResourceSource
 			BAR0)
-		Interrupt (ResourceConsumer,
-			Level, ActiveHigh, Shared, , , ) {14}
+		// Disabled due to IRQ storm: http://crosbug.com/p/29548
+		//Interrupt (ResourceConsumer,
+		//	Level, ActiveHigh, Shared, , , ) {14}
 	})
 
 	Method (_CRS, 0, NotSerialized)
diff --git a/src/soc/intel/broadwell/acpi/lpc.asl b/src/soc/intel/broadwell/acpi/lpc.asl
index 2f27d9b252..ae634a3fd6 100644
--- a/src/soc/intel/broadwell/acpi/lpc.asl
+++ b/src/soc/intel/broadwell/acpi/lpc.asl
@@ -27,10 +27,12 @@ Device (LPCB)
 	OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
 	Field (LPC0, AnyAcc, NoLock, Preserve)
 	{
+		Offset (0x02),
+		PDID,	16,	// Device ID
 		Offset (0x40),
 		PMBS,	16,	// PMBASE
 		Offset (0x48),
-		GPBS,   16,	// GPIOBASE
+		GPBS,	16,	// GPIOBASE
 		Offset (0x60),	// Interrupt Routing Registers
 		PRTA,	8,
 		PRTB,	8,
diff --git a/src/soc/intel/broadwell/acpi/pch.asl b/src/soc/intel/broadwell/acpi/pch.asl
index c48449363e..e40c04269a 100644
--- a/src/soc/intel/broadwell/acpi/pch.asl
+++ b/src/soc/intel/broadwell/acpi/pch.asl
@@ -39,11 +39,29 @@ Scope (\)
 		, 5,
 		HPTE, 1,	// Address Enable
 	}
+
+	/*
+	 * Check PCH type
+	 * Return 1 if PCH is WildcatPoint
+	 * Return 0 if PCH is LynxPoint
+	 */
+	Method (ISWP)
+	{
+		And (\_SB.PCI0.LPCB.PDID, 0xfff0, Local0)
+		If (LEqual (Local0, 0x9cc0)) {
+			Return (1)
+		} Else {
+			Return (0)
+		}
+	}
 }
 
 // High Definition Audio (Azalia) 0:1b.0
 #include "hda.asl"
 
+// ADSP/SST 0:13.0
+#include "adsp.asl"
+
 // PCI Express Ports 0:1c.x
 #include "pcie.asl"
 
diff --git a/src/soc/intel/broadwell/acpi/serialio.asl b/src/soc/intel/broadwell/acpi/serialio.asl
index 532eb50764..6b42d54024 100644
--- a/src/soc/intel/broadwell/acpi/serialio.asl
+++ b/src/soc/intel/broadwell/acpi/serialio.asl
@@ -22,6 +22,46 @@
 // Serial IO Device BAR0 and BAR1 is 4KB
 #define SIO_BAR_LEN 0x1000
 
+// Put SerialIO device in D0 state
+// Arg0 - BAR1 of device
+// Arg1 - Set if device is in ACPI mode
+Method (LPD0, 2, Serialized)
+{
+	// PCI mode devices will be handled by OS PCI bus driver
+	If (LEqual (Arg1, 0)) {
+		Return
+	}
+
+	OperationRegion (SPRT, SystemMemory, Add (Arg0, 0x84), 4)
+	Field (SPRT, DWordAcc, NoLock, Preserve)
+	{
+		SPCS, 32
+	}
+
+	And (SPCS, 0xFFFFFFFC, SPCS)
+	Store (SPCS, Local0) // Read back after writing
+}
+
+// Put SerialIO device in D3 state
+// Arg0 - BAR1 of device
+// Arg1 - Set if device is in ACPI mode
+Method (LPD3, 2, Serialized)
+{
+	// PCI mode devices will be handled by OS PCI bus driver
+	If (LEqual (Arg1, 0)) {
+		Return
+	}
+
+	OperationRegion (SPRT, SystemMemory, Add (Arg0, 0x84), 4)
+	Field (SPRT, DWordAcc, NoLock, Preserve)
+	{
+		SPCS, 32
+	}
+
+	Or (SPCS, 0x3, SPCS)
+	Store (SPCS, Local0) // Read back after writing
+}
+
 // Serial IO Resource Consumption for BAR1
 Device (SIOR)
 {
@@ -152,11 +192,22 @@ Device (SDMA)
 Device (I2C0)
 {
 	// Serial IO I2C0 Controller
-	Name (_HID, "INT33C2")
-	Name (_CID, "INT33C2")
+	Method (_HID)
+	{
+		If (\ISWP ()) {
+			// WildcatPoint
+			Return ("INT3432")
+		}
+
+		// LynxPoint-LP
+		Return ("INT33C2")
+	}
 	Name (_UID, 1)
 	Name (_ADR, 0x00150001)
 
+	Name (SSCN, Package () { 432, 507, 9 })
+	Name (FMCN, Package () { 72, 160, 9 })
+
 	// BAR0 is assigned during PCI enumeration and saved into NVS
 	Name (RBUF, ResourceTemplate ()
 	{
@@ -167,9 +218,8 @@ Device (I2C0)
 	// DMA channels are only used if Serial IO DMA controller is enabled
 	Name (DBUF, ResourceTemplate ()
 	{
-		// TODO: Need to update IASL to support FixedDMA
-		//FixedDMA (0x18, 4, Width32Bit, DMA1) // Tx
-		//FixedDMA (0x19, 5, Width32Bit, DMA2) // Rx
+		FixedDMA (0x18, 4, Width32Bit, DMA1) // Tx
+		FixedDMA (0x19, 5, Width32Bit, DMA2) // Rx
 	})
 
 	Method (_CRS, 0, NotSerialized)
@@ -198,16 +248,37 @@ Device (I2C0)
 			Return (0xF)
 		}
 	}
+
+	Method (_PS0, 0, Serialized)
+	{
+		^^LPD0 (\S1B1, \S1EN)
+	}
+
+	Method (_PS3, 0, Serialized)
+	{
+		^^LPD3 (\S1B1, \S1EN)
+	}
 }
 
 Device (I2C1)
 {
 	// Serial IO I2C1 Controller
-	Name (_HID, "INT33C3")
-	Name (_CID, "INT33C3")
+	Method (_HID)
+	{
+		If (\ISWP ()) {
+			// WildcatPoint
+			Return ("INT3433")
+		}
+
+		// LynxPoint-LP
+		Return ("INT33C3")
+	}
 	Name (_UID, 1)
 	Name (_ADR, 0x00150002)
 
+	Name (SSCN, Package () { 432, 507, 9 })
+	Name (FMCN, Package () { 72, 160, 9 })
+
 	// BAR0 is assigned during PCI enumeration and saved into NVS
 	Name (RBUF, ResourceTemplate ()
 	{
@@ -218,9 +289,8 @@ Device (I2C1)
 	// DMA channels are only used if Serial IO DMA controller is enabled
 	Name (DBUF, ResourceTemplate ()
 	{
-		// TODO: Need to update IASL to support FixedDMA
-		//FixedDMA (0x1A, 6, Width32Bit, DMA1) // Tx
-		//FixedDMA (0x1B, 7, Width32Bit, DMA2) // Rx
+		FixedDMA (0x1A, 6, Width32Bit, DMA1) // Tx
+		FixedDMA (0x1B, 7, Width32Bit, DMA2) // Rx
 	})
 
 	Method (_CRS, 0, NotSerialized)
@@ -249,13 +319,31 @@ Device (I2C1)
 			Return (0xF)
 		}
 	}
+
+	Method (_PS0, 0, Serialized)
+	{
+		^^LPD0 (\S2B1, \S2EN)
+	}
+
+	Method (_PS3, 0, Serialized)
+	{
+		^^LPD3 (\S2B1, \S2EN)
+	}
 }
 
 Device (SPI0)
 {
 	// Serial IO SPI0 Controller
-	Name (_HID, "INT33C0")
-	Name (_CID, "INT33C0")
+	Method (_HID)
+	{
+		If (\ISWP ()) {
+			// WildcatPoint
+			Return ("INT3430")
+		}
+
+		// LynxPoint-LP
+		Return ("INT33C0")
+	}
 	Name (_UID, 1)
 	Name (_ADR, 0x00150003)
 
@@ -287,13 +375,31 @@ Device (SPI0)
 			Return (0xF)
 		}
 	}
+
+	Method (_PS0, 0, Serialized)
+	{
+		^^LPD0 (\S3B1, \S3EN)
+	}
+
+	Method (_PS3, 0, Serialized)
+	{
+		^^LPD3 (\S3B1, \S3EN)
+	}
 }
 
 Device (SPI1)
 {
 	// Serial IO SPI1 Controller
-	Name (_HID, "INT33C1")
-	Name (_CID, "INT33C1")
+	Method (_HID)
+	{
+		If (\ISWP ()) {
+			// WildcatPoint
+			Return ("INT3431")
+		}
+
+		// LynxPoint-LP
+		Return ("INT33C1")
+	}
 	Name (_UID, 1)
 	Name (_ADR, 0x00150004)
 
@@ -307,9 +413,8 @@ Device (SPI1)
 	// DMA channels are only used if Serial IO DMA controller is enabled
 	Name (DBUF, ResourceTemplate ()
 	{
-		// TODO: Need to update IASL to support FixedDMA
-		//FixedDMA (0x10, 0, Width32Bit, DMA1) // Tx
-		//FixedDMA (0x11, 1, Width32Bit, DMA2) // Rx
+		FixedDMA (0x10, 0, Width32Bit, DMA1) // Tx
+		FixedDMA (0x11, 1, Width32Bit, DMA2) // Rx
 	})
 
 	Method (_CRS, 0, NotSerialized)
@@ -338,13 +443,31 @@ Device (SPI1)
 			Return (0xF)
 		}
 	}
+
+	Method (_PS0, 0, Serialized)
+	{
+		^^LPD0 (\S4B1, \S4EN)
+	}
+
+	Method (_PS3, 0, Serialized)
+	{
+		^^LPD3 (\S4B1, \S4EN)
+	}
 }
 
 Device (UAR0)
 {
 	// Serial IO UART0 Controller
-	Name (_HID, "INT33C4")
-	Name (_CID, "INT33C4")
+	Method (_HID)
+	{
+		If (\ISWP ()) {
+			// WildcatPoint
+			Return ("INT3434")
+		}
+
+		// LynxPoint-LP
+		Return ("INT33C4")
+	}
 	Name (_UID, 1)
 	Name (_ADR, 0x00150005)
 
@@ -358,9 +481,8 @@ Device (UAR0)
 	// DMA channels are only used if Serial IO DMA controller is enabled
 	Name (DBUF, ResourceTemplate ()
 	{
-		// TODO: Need to update IASL to support FixedDMA
-		//FixedDMA (0x16, 2, Width32Bit, DMA1) // Tx
-		//FixedDMA (0x17, 3, Width32Bit, DMA2) // Rx
+		FixedDMA (0x16, 2, Width32Bit, DMA1) // Tx
+		FixedDMA (0x17, 3, Width32Bit, DMA2) // Rx
 	})
 
 	Method (_CRS, 0, NotSerialized)
@@ -389,13 +511,31 @@ Device (UAR0)
 			Return (0xF)
 		}
 	}
+
+	Method (_PS0, 0, Serialized)
+	{
+		^^LPD0 (\S5B1, \S5EN)
+	}
+
+	Method (_PS3, 0, Serialized)
+	{
+		^^LPD3 (\S5B1, \S5EN)
+	}
 }
 
 Device (UAR1)
 {
 	// Serial IO UART1 Controller
-	Name (_HID, "INT33C5")
-	Name (_CID, "INT33C5")
+	Method (_HID)
+	{
+		If (\ISWP ()) {
+			// WildcatPoint
+			Return ("INT3435")
+		}
+
+		// LynxPoint-LP
+		Return ("INT33C5")
+	}
 	Name (_UID, 1)
 	Name (_ADR, 0x00150006)
 
@@ -427,12 +567,31 @@ Device (UAR1)
 			Return (0xF)
 		}
 	}
+
+	Method (_PS0, 0, Serialized)
+	{
+		^^LPD0 (\S6B1, \S6EN)
+	}
+
+	Method (_PS3, 0, Serialized)
+	{
+		^^LPD3 (\S6B1, \S6EN)
+	}
 }
 
 Device (SDIO)
 {
 	// Serial IO SDIO Controller
-	Name (_HID, "INT33C6")
+	Method (_HID)
+	{
+		If (\ISWP ()) {
+			// WildcatPoint
+			Return ("INT3436")
+		}
+
+		// LynxPoint-LP
+		Return ("INT33C6")
+	}
 	Name (_CID, "PNP0D40")
 	Name (_UID, 1)
 	Name (_ADR, 0x00170000)