diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-05-28 16:26:43 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-04 09:20:52 +0000 |
| commit | 05498a254d5364efb669f63aa4b042c91c123727 (patch) | |
| tree | 21fe95cd426c1da7a2ea54f44bfcb1566731308d /src/soc/intel/broadwell/acpi | |
| parent | e7f4beca19d538c47208b8a1b984cf0e39ff02b4 (diff) | |
src/soc: Get rid of whitespace before tab
Change-Id: Ia024fb418f02d90c38b9a35ff819c607b9ac4965
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/broadwell/acpi')
| -rw-r--r-- | src/soc/intel/broadwell/acpi/pch.asl | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/acpi/pci_irqs.asl | 8 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/broadwell/acpi/pch.asl b/src/soc/intel/broadwell/acpi/pch.asl index 76804f8b8a..ef0eaba476 100644 --- a/src/soc/intel/broadwell/acpi/pch.asl +++ b/src/soc/intel/broadwell/acpi/pch.asl @@ -31,7 +31,7 @@ Scope (\) Field (RCRB, DWordAcc, Lock, Preserve) { Offset (0x3404), // High Performance Timer Configuration - HPAS, 2, // Address Select + HPAS, 2, // Address Select , 5, HPTE, 1, // Address Enable } diff --git a/src/soc/intel/broadwell/acpi/pci_irqs.asl b/src/soc/intel/broadwell/acpi/pci_irqs.asl index 6565334fdf..44263ea6ab 100644 --- a/src/soc/intel/broadwell/acpi/pci_irqs.asl +++ b/src/soc/intel/broadwell/acpi/pci_irqs.asl @@ -29,11 +29,11 @@ Method(_PRT) Package() { 0x001cffff, 1, 0, 17 }, Package() { 0x001cffff, 2, 0, 18 }, Package() { 0x001cffff, 3, 0, 19 }, - // EHCI 0:1d.0 + // EHCI 0:1d.0 Package() { 0x001dffff, 0, 0, 19 }, // Audio DSP (Smart Sound) 0:13.0 Package() { 0x0013ffff, 0, 0, 23 }, - // XHCI 0:14.0 + // XHCI 0:14.0 Package() { 0x0014ffff, 0, 0, 18 }, // LPC devices 0:1f.0 Package() { 0x001fffff, 0, 0, 22 }, @@ -61,11 +61,11 @@ Method(_PRT) Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI 0:1d.0 + // EHCI 0:1d.0 Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, // Audio DSP (Smart Sound) 0:13.0 Package() { 0x0013ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - // XHCI 0:14.0 + // XHCI 0:14.0 Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, // LPC device 0:1f.0 Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, |