soc/intel/broadwell: Relocate PCH ACPI files

Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: I7f87085c70149d02c544e2d43e1bdb58c7502d6d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46754
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

15 files changed, 0 insertions, 2309 deletions

diff --git a/src/soc/intel/broadwell/acpi/adsp.asl b/src/soc/intel/broadwell/acpi/adsp.asl
deleted file mode 100644
index 435db4d404..0000000000
--- a/src/soc/intel/broadwell/acpi/adsp.asl
+++ /dev/null
@@ -1,56 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Device (ADSP)
-{
-	Method (_HID, 0, Serialized)
-	{
-		If (\ISWP ()) {
-			// WildcatPoint
-			Return ("INT3438")
-		}
-
-		// LynxPoint-LP
-		Return ("INT33C8")
-	}
-	Name (_UID, 1)
-	Name (_DDN, "Intel Smart Sound Technology")
-
-	Name (RBUF, ResourceTemplate ()
-	{
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00100000, BAR0)
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR1)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {3}
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		// Update BAR address and length if set in NVS
-		If (LNotEqual (\S8B0, Zero)) {
-			CreateDwordField (^RBUF, ^BAR0._BAS, B8A0)
-			CreateDwordField (^RBUF, ^BAR1._BAS, B8A1)
-			Store (\S8B0, B8A0)
-			Store (\S8B1, B8A1)
-		}
-
-		Return (RBUF)
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		If (LEqual (\S8EN, 0)) {
-			Return (0x0)
-		} Else {
-			Return (0xF)
-		}
-	}
-
-	Device (I2S0)
-	{
-		Name (_ADR, 0)
-	}
-
-	Device (I2S1)
-	{
-		Name (_ADR, 1)
-	}
-}
diff --git a/src/soc/intel/broadwell/acpi/device_nvs.asl b/src/soc/intel/broadwell/acpi/device_nvs.asl
deleted file mode 100644
index 76cdafc3c0..0000000000
--- a/src/soc/intel/broadwell/acpi/device_nvs.asl
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Device Enabled in ACPI Mode */
-
-S0EN,	8,	// DMA Enable
-S1EN,	8,	// I2C0 Enable
-S2EN,	8,	// I2C1 Enable
-S3EN,	8,	// SPI0 Enable
-S4EN,	8,	// SPI1 Enable
-S5EN,	8,	// UART0 Enable
-S6EN,	8,	// UART1 Enable
-S7EN,	8,	// SDIO Enable
-S8EN,	8,	// ADSP Enable
-
-/* BAR 0 */
-
-S0B0,	32,	// DMA BAR0
-S1B0,	32,	// I2C0 BAR0
-S2B0,	32,	// I2C1 BAR0
-S3B0,	32,	// SPI0 BAR0
-S4B0,	32,	// SPI1 BAR0
-S5B0,	32,	// UART0 BAR0
-S6B0,	32,	// UART1 BAR0
-S7B0,	32,	// SDIO BAR0
-S8B0,	32,	// ADSP BAR0
-
-/* BAR 1 */
-
-S0B1,	32,	// DMA BAR1
-S1B1,	32,	// I2C0 BAR1
-S2B1,	32,	// I2C1 BAR1
-S3B1,	32,	// SPI0 BAR1
-S4B1,	32,	// SPI1 BAR1
-S5B1,	32,	// UART0 BAR1
-S6B1,	32,	// UART1 BAR1
-S7B1,	32,	// SDIO BAR1
-S8B1,	32,	// ADSP BAR1
diff --git a/src/soc/intel/broadwell/acpi/ehci.asl b/src/soc/intel/broadwell/acpi/ehci.asl
deleted file mode 100644
index c02bc1a179..0000000000
--- a/src/soc/intel/broadwell/acpi/ehci.asl
+++ /dev/null
@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-// EHCI Controller 0:1d.0
-
-Device (EHCI)
-{
-	Name(_ADR, 0x001d0000)
-	Name (_PRW, Package(){ 0x6d, 3 })
-
-	// Leave USB ports on for to allow Wake from USB
-
-	Method(_S3D,0)	// Highest D State in S3 State
-	{
-		Return (2)
-	}
-
-	Method(_S4D,0)	// Highest D State in S4 State
-	{
-		Return (2)
-	}
-
-	Device (HUB7)
-	{
-		Name (_ADR, 0x00000000)
-
-		// How many are there?
-		Device (PRT1) { Name (_ADR, 1) } // USB Port 0
-		Device (PRT2) { Name (_ADR, 2) } // USB Port 1
-		Device (PRT3) { Name (_ADR, 3) } // USB Port 2
-		Device (PRT4) { Name (_ADR, 4) } // USB Port 3
-		Device (PRT5) { Name (_ADR, 5) } // USB Port 4
-		Device (PRT6) { Name (_ADR, 6) } // USB Port 5
-	}
-}
diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/acpi/globalnvs.asl
deleted file mode 100644
index 3c6c5f5998..0000000000
--- a/src/soc/intel/broadwell/acpi/globalnvs.asl
+++ /dev/null
@@ -1,91 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Global Variables */
-
-Name (\PICM, 0)		// IOAPIC/8259
-
-/*
- * Global ACPI memory region. This region is used for passing information
- * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
- * Since we don't know where this will end up in memory at ACPI compile time,
- * we have to fix it up in coreboot's ACPI creation phase.
- */
-
-External(NVSA)
-OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
-Field (GNVS, ByteAcc, NoLock, Preserve)
-{
-	/* Miscellaneous */
-	Offset (0x00),
-	OSYS,	16,	// 0x00 - Operating System
-	SMIF,	8,	// 0x02 - SMI function
-	PRM0,	8,	// 0x03 - SMI function parameter
-	PRM1,	8,	// 0x04 - SMI function parameter
-	SCIF,	8,	// 0x05 - SCI function
-	PRM2,	8,	// 0x06 - SCI function parameter
-	PRM3,	8,	// 0x07 - SCI function parameter
-	LCKF,	8,	// 0x08 - Global Lock function for EC
-	PRM4,	8,	// 0x09 - Lock function parameter
-	PRM5,	8,	// 0x0a - Lock function parameter
-	PCNT,	8,	// 0x0b - Processor Count
-	PPCM,	8,	// 0x0c - Max PPC State
-	TMPS,	8,	// 0x0d - Temperature Sensor ID
-	TLVL,	8,	// 0x0e - Throttle Level Limit
-	FLVL,	8,	// 0x0f - Current FAN Level
-	TCRT,	8,	// 0x10 - Critical Threshold
-	TPSV,	8,	// 0x11 - Passive Threshold
-	TMAX,	8,	// 0x12 - CPU Tj_max
-	S5U0,	8,	// 0x13 - Enable USB in S5
-	S3U0,	8,	// 0x14 - Enable USB in S3
-	S33G,	8,	// 0x15 - Enable 3G in S3
-	LIDS,	8,	// 0x16 - LID State
-	PWRS,	8,	// 0x17 - AC Power State
-	CMEM,	32,	// 0x18 - 0x1b - CBMEM TOC
-	CBMC,	32,	// 0x1c - 0x1f - coreboot Memory Console
-	PM1I,	64,	// 0x20 - 0x27 - PM1 wake status bit
-	GPEI,	64,	// 0x28 - 0x2f - GPE wake status bit
-
-	/* ChromeOS specific */
-	Offset (0x100),
-	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
-
-	/* Device specific */
-	Offset (0x1000),
-	#include "device_nvs.asl"
-}
-
-/* Set flag to enable USB charging in S3 */
-Method (S3UE)
-{
-	Store (One, \S3U0)
-}
-
-/* Set flag to disable USB charging in S3 */
-Method (S3UD)
-{
-	Store (Zero, \S3U0)
-}
-
-/* Set flag to enable USB charging in S5 */
-Method (S5UE)
-{
-	Store (One, \S5U0)
-}
-
-/* Set flag to disable USB charging in S5 */
-Method (S5UD)
-{
-	Store (Zero, \S5U0)
-}
-
-/* Set flag to enable 3G module in S3 */
-Method (S3GE)
-{
-	Store (One, \S33G)
-}
-
-/* Set flag to disable 3G module in S3 */
-Method (S3GD)
-{
-	Store (Zero, \S33G)
-}
diff --git a/src/soc/intel/broadwell/acpi/gpio.asl b/src/soc/intel/broadwell/acpi/gpio.asl
deleted file mode 100644
index cfe0aed0b2..0000000000
--- a/src/soc/intel/broadwell/acpi/gpio.asl
+++ /dev/null
@@ -1,125 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Device (GPIO)
-{
-	// GPIO Controller
-	Method (_HID)
-	{
-		If (\ISWP ()) {
-			// WildcatPoint
-			Return ("INT3437")
-		}
-
-		// LynxPoint-LP
-		Return ("INT33C7")
-	}
-	Name (_UID, 1)
-
-	Name (RBUF, ResourceTemplate()
-	{
-		DWordIo (ResourceProducer,
-			MinFixed,    // IsMinFixed
-			MaxFixed,    // IsMaxFixed
-			PosDecode,   // Decode
-			EntireRange, // ISARanges
-			0x00000000,  // AddressGranularity
-			0x00000000,  // AddressMinimum
-			0x00000000,  // AddressMaximum
-			0x00000000,  // AddressTranslation
-			0x00000000,  // RangeLength
-			,            // ResourceSourceIndex
-			,            // ResourceSource
-			BAR0)
-		// Disabled due to IRQ storm: http://crosbug.com/p/29548
-		//Interrupt (ResourceConsumer,
-		//	Level, ActiveHigh, Shared, , , ) {14}
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		CreateDwordField (^RBUF, ^BAR0._MIN, BMIN)
-		CreateDwordField (^RBUF, ^BAR0._MAX, BMAX)
-		CreateDwordField (^RBUF, ^BAR0._LEN, BLEN)
-
-		Store (GPIO_BASE_SIZE, BLEN)
-		Store (GPIO_BASE_ADDRESS, BMIN)
-		Store (Subtract (Add (GPIO_BASE_ADDRESS,
-				      GPIO_BASE_SIZE), 1), BMAX)
-
-		Return (RBUF)
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		Return (0xF)
-	}
-
-	// GWAK: Setup GPIO as ACPI GPE for Wake
-	// Arg0: GPIO Number
-	Method (GWAK, 1, Serialized)
-	{
-		// Local0 = GPIO Base Address
-		Store (And (GPBS, Not(0x1)), Local0)
-
-		// Local1 = BANK, Local2 = OFFSET
-		Divide (Arg0, 32, Local2, Local1)
-
-		//
-		// Set OWNER to ACPI
-		//
-
-		// Local3 = GPIOBASE + GPIO_OWN(BANK)
-		Store (Add (Local0, Multiply (Local1, 0x4)), Local3)
-
-		// GPIO_OWN(BANK)
-		OperationRegion (IOWN, SystemIO, Local3, 4)
-		Field (IOWN, AnyAcc, NoLock, Preserve) {
-			GOWN, 32,
-		}
-
-		// GPIO_OWN[GPIO] = 0 (ACPI)
-		Store (And (GOWN, Not (ShiftLeft (0x1, Local2))), GOWN)
-
-		//
-		// Set ROUTE to SCI
-		//
-
-		// Local3 = GPIOBASE + GPIO_ROUTE(BANK)
-		Store (Add (Add (Local0, 0x30), Multiply (Local1, 0x4)), Local3)
-
-		// GPIO_ROUTE(BANK)
-		OperationRegion (IROU, SystemIO, Local3, 4)
-		Field (IROU, AnyAcc, NoLock, Preserve) {
-			GROU, 32,
-		}
-
-		// GPIO_ROUTE[GPIO] = 0 (SCI)
-		Store (And (GROU, Not (ShiftLeft (0x1, Local2))), GROU)
-
-		//
-		// Set GPnCONFIG to GPIO|INPUT|INVERT
-		//
-
-		// Local3 = GPIOBASE + GPnCONFIG0(GPIO)
-		Store (Add (Add (Local0, 0x100), Multiply (Arg0, 0x8)), Local3)
-
-		// GPnCONFIG(GPIO)
-		OperationRegion (GPNC, SystemIO, Local3, 8)
-		Field (GPNC, AnyAcc, NoLock, Preserve) {
-			GMOD, 1,  // MODE:   0=NATIVE 1=GPIO
-			, 1,
-			GIOS, 1,  // IO_SEL: 0=OUTPUT 1=INPUT
-			GINV, 1,  // INVERT: 0=NORMAL 1=INVERT
-			GLES, 1,  // LxEB:   0=EDGE 1=LEVEL
-			, 24,
-			ILVL, 1,  // INPUT:  0=LOW 1=HIGH
-			OLVL, 1,  // OUTPUT: 0=LOW 1=HIGH
-			GPWP, 2,  // PULLUP: 00=NONE 01=DOWN 10=UP 11=INVALID
-			ISEN, 1,  // SENSE:  0=ENABLE 1=DISABLE
-		}
-
-		Store (0x1, GMOD) // GPIO
-		Store (0x1, GIOS) // INPUT
-		Store (0x1, GINV) // INVERT
-	}
-}
diff --git a/src/soc/intel/broadwell/acpi/hda.asl b/src/soc/intel/broadwell/acpi/hda.asl
deleted file mode 100644
index a6f0d7b252..0000000000
--- a/src/soc/intel/broadwell/acpi/hda.asl
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Intel PCH HDA */
-
-// Intel High Definition Audio (Azalia) 0:1b.0
-
-Device (HDEF)
-{
-	Name (_ADR, 0x001b0000)
-	Name (_PRW, Package () { 0x6d, 3 })
-}
diff --git a/src/soc/intel/broadwell/acpi/irqlinks.asl b/src/soc/intel/broadwell/acpi/irqlinks.asl
deleted file mode 100644
index 0661ff8fce..0000000000
--- a/src/soc/intel/broadwell/acpi/irqlinks.asl
+++ /dev/null
@@ -1,473 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Device (LNKA)
-{
-	Name (_HID, EISAID("PNP0C0F"))
-	Name (_UID, 1)
-
-	// Disable method
-	Method (_DIS, 0, Serialized)
-	{
-		Store (0x80, PRTA)
-	}
-
-	// Possible Resource Settings for this Link
-	Name (_PRS, ResourceTemplate()
-	{
-		IRQ (Level, ActiveLow, Shared)
-			{ 3, 4, 5, 6, 7, 10, 12, 14, 15 }
-	})
-
-	// Current Resource Settings for this link
-	Method (_CRS, 0, Serialized)
-	{
-		Name (RTLA, ResourceTemplate()
-		{
-			IRQ (Level, ActiveLow, Shared) {}
-		})
-		CreateWordField (RTLA, 1, IRQ0)
-
-		// Clear the WordField
-		Store (Zero, IRQ0)
-
-		// Set the bit from PRTA
-		ShiftLeft (1, And (PRTA, 0x0f), IRQ0)
-
-		Return (RTLA)
-	}
-
-	// Set Resource Setting for this IRQ link
-	Method (_SRS, 1, Serialized)
-	{
-		CreateWordField (Arg0, 1, IRQ0)
-
-		// Which bit is set?
-		FindSetRightBit (IRQ0, Local0)
-
-		Decrement(Local0)
-		Store (Local0, PRTA)
-	}
-
-	// Status
-	Method (_STA, 0, Serialized)
-	{
-		If(And (PRTA, 0x80)) {
-			Return (0x9)
-		} Else {
-			Return (0xb)
-		}
-	}
-}
-
-Device (LNKB)
-{
-	Name (_HID, EISAID("PNP0C0F"))
-	Name (_UID, 2)
-
-	// Disable method
-	Method (_DIS, 0, Serialized)
-	{
-		Store (0x80, PRTB)
-	}
-
-	// Possible Resource Settings for this Link
-	Name (_PRS, ResourceTemplate()
-	{
-		IRQ (Level, ActiveLow, Shared)
-			{ 3, 4, 5, 6, 7, 11, 12, 14, 15 }
-	})
-
-	// Current Resource Settings for this link
-	Method (_CRS, 0, Serialized)
-	{
-		Name (RTLB, ResourceTemplate()
-		{
-			IRQ (Level, ActiveLow, Shared) {}
-		})
-		CreateWordField (RTLB, 1, IRQ0)
-
-		// Clear the WordField
-		Store (Zero, IRQ0)
-
-		// Set the bit from PRTB
-		ShiftLeft (1, And (PRTB, 0x0f), IRQ0)
-
-		Return (RTLB)
-	}
-
-	// Set Resource Setting for this IRQ link
-	Method (_SRS, 1, Serialized)
-	{
-		CreateWordField (Arg0, 1, IRQ0)
-
-		// Which bit is set?
-		FindSetRightBit (IRQ0, Local0)
-
-		Decrement(Local0)
-		Store (Local0, PRTB)
-	}
-
-	// Status
-	Method (_STA, 0, Serialized)
-	{
-		If(And (PRTB, 0x80)) {
-			Return (0x9)
-		} Else {
-			Return (0xb)
-		}
-	}
-}
-
-Device (LNKC)
-{
-	Name (_HID, EISAID("PNP0C0F"))
-	Name (_UID, 3)
-
-	// Disable method
-	Method (_DIS, 0, Serialized)
-	{
-		Store (0x80, PRTC)
-	}
-
-	// Possible Resource Settings for this Link
-	Name (_PRS, ResourceTemplate()
-	{
-		IRQ (Level, ActiveLow, Shared)
-			{ 3, 4, 5, 6, 7, 10, 12, 14, 15 }
-	})
-
-	// Current Resource Settings for this link
-	Method (_CRS, 0, Serialized)
-	{
-		Name (RTLC, ResourceTemplate()
-		{
-			IRQ (Level, ActiveLow, Shared) {}
-		})
-		CreateWordField (RTLC, 1, IRQ0)
-
-		// Clear the WordField
-		Store (Zero, IRQ0)
-
-		// Set the bit from PRTC
-		ShiftLeft (1, And (PRTC, 0x0f), IRQ0)
-
-		Return (RTLC)
-	}
-
-	// Set Resource Setting for this IRQ link
-	Method (_SRS, 1, Serialized)
-	{
-		CreateWordField (Arg0, 1, IRQ0)
-
-		// Which bit is set?
-		FindSetRightBit (IRQ0, Local0)
-
-		Decrement(Local0)
-		Store (Local0, PRTC)
-	}
-
-	// Status
-	Method (_STA, 0, Serialized)
-	{
-		If(And (PRTC, 0x80)) {
-			Return (0x9)
-		} Else {
-			Return (0xb)
-		}
-	}
-}
-
-Device (LNKD)
-{
-	Name (_HID, EISAID("PNP0C0F"))
-	Name (_UID, 4)
-
-	// Disable method
-	Method (_DIS, 0, Serialized)
-	{
-		Store (0x80, PRTD)
-	}
-
-	// Possible Resource Settings for this Link
-	Name (_PRS, ResourceTemplate()
-	{
-		IRQ (Level, ActiveLow, Shared)
-			{ 3, 4, 5, 6, 7, 11, 12, 14, 15 }
-	})
-
-	// Current Resource Settings for this link
-	Method (_CRS, 0, Serialized)
-	{
-		Name (RTLD, ResourceTemplate()
-		{
-			IRQ (Level, ActiveLow, Shared) {}
-		})
-		CreateWordField (RTLD, 1, IRQ0)
-
-		// Clear the WordField
-		Store (Zero, IRQ0)
-
-		// Set the bit from PRTD
-		ShiftLeft (1, And (PRTD, 0x0f), IRQ0)
-
-		Return (RTLD)
-	}
-
-	// Set Resource Setting for this IRQ link
-	Method (_SRS, 1, Serialized)
-	{
-		CreateWordField (Arg0, 1, IRQ0)
-
-		// Which bit is set?
-		FindSetRightBit (IRQ0, Local0)
-
-		Decrement(Local0)
-		Store (Local0, PRTD)
-	}
-
-	// Status
-	Method (_STA, 0, Serialized)
-	{
-		If(And (PRTD, 0x80)) {
-			Return (0x9)
-		} Else {
-			Return (0xb)
-		}
-	}
-}
-
-Device (LNKE)
-{
-	Name (_HID, EISAID("PNP0C0F"))
-	Name (_UID, 5)
-
-	// Disable method
-	Method (_DIS, 0, Serialized)
-	{
-		Store (0x80, PRTE)
-	}
-
-	// Possible Resource Settings for this Link
-	Name (_PRS, ResourceTemplate()
-	{
-		IRQ (Level, ActiveLow, Shared)
-			{ 3, 4, 5, 6, 7, 10, 12, 14, 15 }
-	})
-
-	// Current Resource Settings for this link
-	Method (_CRS, 0, Serialized)
-	{
-		Name (RTLE, ResourceTemplate()
-		{
-			IRQ (Level, ActiveLow, Shared) {}
-		})
-		CreateWordField (RTLE, 1, IRQ0)
-
-		// Clear the WordField
-		Store (Zero, IRQ0)
-
-		// Set the bit from PRTE
-		ShiftLeft (1, And (PRTE, 0x0f), IRQ0)
-
-		Return (RTLE)
-	}
-
-	// Set Resource Setting for this IRQ link
-	Method (_SRS, 1, Serialized)
-	{
-		CreateWordField (Arg0, 1, IRQ0)
-
-		// Which bit is set?
-		FindSetRightBit (IRQ0, Local0)
-
-		Decrement(Local0)
-		Store (Local0, PRTE)
-	}
-
-	// Status
-	Method (_STA, 0, Serialized)
-	{
-		If(And (PRTE, 0x80)) {
-			Return (0x9)
-		} Else {
-			Return (0xb)
-		}
-	}
-}
-
-Device (LNKF)
-{
-	Name (_HID, EISAID("PNP0C0F"))
-	Name (_UID, 6)
-
-	// Disable method
-	Method (_DIS, 0, Serialized)
-	{
-		Store (0x80, PRTF)
-	}
-
-	// Possible Resource Settings for this Link
-	Name (_PRS, ResourceTemplate()
-	{
-		IRQ (Level, ActiveLow, Shared)
-			{ 3, 4, 5, 6, 7, 11, 12, 14, 15 }
-	})
-
-	// Current Resource Settings for this link
-	Method (_CRS, 0, Serialized)
-	{
-		Name (RTLF, ResourceTemplate()
-		{
-			IRQ (Level, ActiveLow, Shared) {}
-		})
-		CreateWordField (RTLF, 1, IRQ0)
-
-		// Clear the WordField
-		Store (Zero, IRQ0)
-
-		// Set the bit from PRTF
-		ShiftLeft (1, And (PRTF, 0x0f), IRQ0)
-
-		Return (RTLF)
-	}
-
-	// Set Resource Setting for this IRQ link
-	Method (_SRS, 1, Serialized)
-	{
-		CreateWordField (Arg0, 1, IRQ0)
-
-		// Which bit is set?
-		FindSetRightBit (IRQ0, Local0)
-
-		Decrement(Local0)
-		Store (Local0, PRTF)
-	}
-
-	// Status
-	Method (_STA, 0, Serialized)
-	{
-		If(And (PRTF, 0x80)) {
-			Return (0x9)
-		} Else {
-			Return (0xb)
-		}
-	}
-}
-
-Device (LNKG)
-{
-	Name (_HID, EISAID("PNP0C0F"))
-	Name (_UID, 7)
-
-	// Disable method
-	Method (_DIS, 0, Serialized)
-	{
-		Store (0x80, PRTG)
-	}
-
-	// Possible Resource Settings for this Link
-	Name (_PRS, ResourceTemplate()
-	{
-		IRQ (Level, ActiveLow, Shared)
-			{ 3, 4, 5, 6, 7, 10, 12, 14, 15 }
-	})
-
-	// Current Resource Settings for this link
-	Method (_CRS, 0, Serialized)
-	{
-		Name (RTLG, ResourceTemplate()
-		{
-			IRQ (Level, ActiveLow, Shared) {}
-		})
-		CreateWordField (RTLG, 1, IRQ0)
-
-		// Clear the WordField
-		Store (Zero, IRQ0)
-
-		// Set the bit from PRTG
-		ShiftLeft (1, And (PRTG, 0x0f), IRQ0)
-
-		Return (RTLG)
-	}
-
-	// Set Resource Setting for this IRQ link
-	Method (_SRS, 1, Serialized)
-	{
-		CreateWordField (Arg0, 1, IRQ0)
-
-		// Which bit is set?
-		FindSetRightBit (IRQ0, Local0)
-
-		Decrement(Local0)
-		Store (Local0, PRTG)
-	}
-
-	// Status
-	Method (_STA, 0, Serialized)
-	{
-		If(And (PRTG, 0x80)) {
-			Return (0x9)
-		} Else {
-			Return (0xb)
-		}
-	}
-}
-
-Device (LNKH)
-{
-	Name (_HID, EISAID("PNP0C0F"))
-	Name (_UID, 8)
-
-	// Disable method
-	Method (_DIS, 0, Serialized)
-	{
-		Store (0x80, PRTH)
-	}
-
-	// Possible Resource Settings for this Link
-	Name (_PRS, ResourceTemplate()
-	{
-		IRQ (Level, ActiveLow, Shared)
-			{ 3, 4, 5, 6, 7, 11, 12, 14, 15 }
-	})
-
-	// Current Resource Settings for this link
-	Method (_CRS, 0, Serialized)
-	{
-		Name (RTLH, ResourceTemplate()
-		{
-			IRQ (Level, ActiveLow, Shared) {}
-		})
-		CreateWordField (RTLH, 1, IRQ0)
-
-		// Clear the WordField
-		Store (Zero, IRQ0)
-
-		// Set the bit from PRTH
-		ShiftLeft (1, And (PRTH, 0x0f), IRQ0)
-
-		Return (RTLH)
-	}
-
-	// Set Resource Setting for this IRQ link
-	Method (_SRS, 1, Serialized)
-	{
-		CreateWordField (Arg0, 1, IRQ0)
-
-		// Which bit is set?
-		FindSetRightBit (IRQ0, Local0)
-
-		Decrement(Local0)
-		Store (Local0, PRTH)
-	}
-
-	// Status
-	Method (_STA, 0, Serialized)
-	{
-		If(And (PRTH, 0x80)) {
-			Return (0x9)
-		} Else {
-			Return (0xb)
-		}
-	}
-}
diff --git a/src/soc/intel/broadwell/acpi/lpc.asl b/src/soc/intel/broadwell/acpi/lpc.asl
deleted file mode 100644
index 5bdfea24ce..0000000000
--- a/src/soc/intel/broadwell/acpi/lpc.asl
+++ /dev/null
@@ -1,186 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-// Intel LPC Bus Device  - 0:1f.0
-
-Device (LPCB)
-{
-	Name (_ADR, 0x001f0000)
-
-	OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
-	Field (LPC0, AnyAcc, NoLock, Preserve)
-	{
-		Offset (0x02),
-		PDID,	16,	// Device ID
-		Offset (0x40),
-		PMBS,	16,	// PMBASE
-		Offset (0x48),
-		GPBS,	16,	// GPIOBASE
-		Offset (0x60),	// Interrupt Routing Registers
-		PRTA,	8,
-		PRTB,	8,
-		PRTC,	8,
-		PRTD,	8,
-		Offset (0x68),
-		PRTE,	8,
-		PRTF,	8,
-		PRTG,	8,
-		PRTH,	8,
-
-		Offset (0x80),	// IO Decode Ranges
-		IOD0,	8,
-		IOD1,	8,
-	}
-
-	Device (DMAC)	// DMA Controller
-	{
-		Name (_HID, EISAID("PNP0200"))
-		Name (_CRS, ResourceTemplate()
-		{
-			IO (Decode16, 0x00, 0x00, 0x01, 0x20)
-			IO (Decode16, 0x81, 0x81, 0x01, 0x11)
-			IO (Decode16, 0x93, 0x93, 0x01, 0x0d)
-			IO (Decode16, 0xc0, 0xc0, 0x01, 0x20)
-			DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 }
-		})
-	}
-
-	Device (FWH)	// Firmware Hub
-	{
-		Name (_HID, EISAID("INT0800"))
-		Name (_CRS, ResourceTemplate()
-		{
-			Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
-		})
-	}
-
-	Device (HPET)
-	{
-		Name (_HID, EISAID("PNP0103"))
-		Name (_CID, 0x010CD041)
-
-		Name (BUF0, ResourceTemplate()
-		{
-			Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0)
-		})
-
-		Method (_STA, 0)	// Device Status
-		{
-			If (HPTE) {
-				// Note: Ancient versions of Windows don't want
-				// to see the HPET in order to work right
-				If (LGreaterEqual(OSYS, 2001)) {
-					Return (0xf)	// Enable and show device
-				} Else {
-					Return (0xb)	// Enable and don't show device
-				}
-			}
-
-			Return (0x0)	// Not enabled, don't show.
-		}
-
-		Method (_CRS, 0, Serialized) // Current resources
-		{
-			If (HPTE) {
-				CreateDWordField (BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)
-				If (Lequal(HPAS, 1)) {
-					Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0)
-				}
-
-				If (Lequal(HPAS, 2)) {
-					Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0)
-				}
-
-				If (Lequal(HPAS, 3)) {
-					Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0)
-				}
-			}
-
-			Return (BUF0)
-		}
-	}
-
-	Device(PIC)	// 8259 Interrupt Controller
-	{
-		Name (_HID,EISAID("PNP0000"))
-		Name (_CRS, ResourceTemplate()
-		{
-			IO (Decode16, 0x20, 0x20, 0x01, 0x02)
-			IO (Decode16, 0x24, 0x24, 0x01, 0x02)
-			IO (Decode16, 0x28, 0x28, 0x01, 0x02)
-			IO (Decode16, 0x2c, 0x2c, 0x01, 0x02)
-			IO (Decode16, 0x30, 0x30, 0x01, 0x02)
-			IO (Decode16, 0x34, 0x34, 0x01, 0x02)
-			IO (Decode16, 0x38, 0x38, 0x01, 0x02)
-			IO (Decode16, 0x3c, 0x3c, 0x01, 0x02)
-			IO (Decode16, 0xa0, 0xa0, 0x01, 0x02)
-			IO (Decode16, 0xa4, 0xa4, 0x01, 0x02)
-			IO (Decode16, 0xa8, 0xa8, 0x01, 0x02)
-			IO (Decode16, 0xac, 0xac, 0x01, 0x02)
-			IO (Decode16, 0xb0, 0xb0, 0x01, 0x02)
-			IO (Decode16, 0xb4, 0xb4, 0x01, 0x02)
-			IO (Decode16, 0xb8, 0xb8, 0x01, 0x02)
-			IO (Decode16, 0xbc, 0xbc, 0x01, 0x02)
-			IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
-			IRQNoFlags () { 2 }
-		})
-	}
-
-	Device(MATH)	// FPU
-	{
-		Name (_HID, EISAID("PNP0C04"))
-		Name (_CRS, ResourceTemplate()
-		{
-			IO (Decode16, 0xf0, 0xf0, 0x01, 0x01)
-			IRQNoFlags() { 13 }
-		})
-	}
-
-	Device(LDRC)	// LPC device: Resource consumption
-	{
-		Name (_HID, EISAID("PNP0C02"))
-		Name (_UID, 2)
-
-		Name (RBUF, ResourceTemplate()
-		{
-			IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO
-			IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO
-			IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status
-			IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved
-			IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved
-			IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved
-			IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
-			IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
-			IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
-			IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS, 0x1, 0xff)
-		})
-
-		Method (_CRS, 0, NotSerialized)
-		{
-			Return (RBUF)
-		}
-	}
-
-	Device (RTC)	// Real Time Clock
-	{
-		Name (_HID, EISAID("PNP0B00"))
-		Name (_CRS, ResourceTemplate()
-		{
-			IO (Decode16, 0x70, 0x70, 1, 8)
-		})
-	}
-
-	Device (TIMR)	// Intel 8254 timer
-	{
-		Name (_HID, EISAID("PNP0100"))
-		Name (_CRS, ResourceTemplate() {
-			IO (Decode16, 0x40, 0x40, 0x01, 0x04)
-			IO (Decode16, 0x50, 0x50, 0x10, 0x04)
-			IRQNoFlags() {0}
-		})
-	}
-
-	#include "gpio.asl"
-	#include "irqlinks.asl"
-	#include <acpi/ec.asl>
-	#include <acpi/superio.asl>
-}
diff --git a/src/soc/intel/broadwell/acpi/pch.asl b/src/soc/intel/broadwell/acpi/pch.asl
deleted file mode 100644
index 07db9f7f24..0000000000
--- a/src/soc/intel/broadwell/acpi/pch.asl
+++ /dev/null
@@ -1,83 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <soc/iomap.h>
-
-Scope (\)
-{
-	// IO-Trap at 0x800. This is the ACPI->SMI communication interface.
-	OperationRegion (IO_T, SystemIO, 0x800, 0x10)
-	Field (IO_T, ByteAcc, NoLock, Preserve)
-	{
-		Offset (0x8),
-		TRP0, 8		// IO-Trap at 0x808
-	}
-
-	// Root Complex Register Block
-	OperationRegion (RCRB, SystemMemory, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
-	Field (RCRB, DWordAcc, Lock, Preserve)
-	{
-		Offset (0x3404), // High Performance Timer Configuration
-		HPAS, 2,	// Address Select
-		, 5,
-		HPTE, 1,	// Address Enable
-	}
-
-	/*
-	 * Check PCH type
-	 * Return 1 if PCH is WildcatPoint
-	 * Return 0 if PCH is LynxPoint
-	 */
-	Method (ISWP)
-	{
-		And (\_SB.PCI0.LPCB.PDID, 0xfff0, Local0)
-		If (LEqual (Local0, 0x9cc0)) {
-			Return (1)
-		} Else {
-			Return (0)
-		}
-	}
-}
-
-// High Definition Audio (Azalia) 0:1b.0
-#include "hda.asl"
-
-// ADSP/SST 0:13.0
-#include "adsp.asl"
-
-// PCI Express Ports 0:1c.x
-#include "pcie.asl"
-
-// USB EHCI 0:1d.0
-#include "ehci.asl"
-
-// USB XHCI 0:14.0
-#include "xhci.asl"
-
-// LPC Bridge 0:1f.0
-#include "lpc.asl"
-
-// SATA 0:1f.2
-#include "sata.asl"
-
-// SMBus 0:1f.3
-#include "smbus.asl"
-
-// Serial IO
-#include "serialio.asl"
-
-Method (_OSC, 4)
-{
-	/* Check for proper GUID */
-	If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
-	{
-		/* Let OS control everything */
-		Return (Arg3)
-	}
-	Else
-	{
-		/* Unrecognized UUID */
-		CreateDWordField (Arg3, 0, CDW1)
-		Or (CDW1, 4, CDW1)
-		Return (Arg3)
-	}
-}
diff --git a/src/soc/intel/broadwell/acpi/pcie.asl b/src/soc/intel/broadwell/acpi/pcie.asl
deleted file mode 100644
index 72993f9372..0000000000
--- a/src/soc/intel/broadwell/acpi/pcie.asl
+++ /dev/null
@@ -1,196 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Intel PCH PCIe support */
-
-Method (IRQM, 1, Serialized) {
-
-	/* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */
-	Name (IQAA, Package() {
-		Package() { 0x0000ffff, 0, 0, 16 },
-		Package() { 0x0000ffff, 1, 0, 17 },
-		Package() { 0x0000ffff, 2, 0, 18 },
-		Package() { 0x0000ffff, 3, 0, 19 } })
-	Name (IQAP, Package() {
-		Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-		Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
-		Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
-		Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } })
-
-	/* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */
-	Name (IQBA, Package() {
-		Package() { 0x0000ffff, 0, 0, 17 },
-		Package() { 0x0000ffff, 1, 0, 18 },
-		Package() { 0x0000ffff, 2, 0, 19 },
-		Package() { 0x0000ffff, 3, 0, 16 } })
-	Name (IQBP, Package() {
-		Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
-		Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
-		Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
-		Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } })
-
-	/* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */
-	Name (IQCA, Package() {
-		Package() { 0x0000ffff, 0, 0, 18 },
-		Package() { 0x0000ffff, 1, 0, 19 },
-		Package() { 0x0000ffff, 2, 0, 16 },
-		Package() { 0x0000ffff, 3, 0, 17 } })
-	Name (IQCP, Package() {
-		Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
-		Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
-		Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
-		Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 } })
-
-	/* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */
-	Name (IQDA, Package() {
-		Package() { 0x0000ffff, 0, 0, 19 },
-		Package() { 0x0000ffff, 1, 0, 16 },
-		Package() { 0x0000ffff, 2, 0, 17 },
-		Package() { 0x0000ffff, 3, 0, 18 } })
-	Name (IQDP, Package() {
-		Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
-		Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
-		Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
-		Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 } })
-
-	Switch (ToInteger (Arg0)) {
-		/* PCIe Root Port 1 and 5 */
-		Case (Package() { 1, 5 }) {
-			If (PICM) {
-				Return (IQAA)
-			} Else {
-				Return (IQAP)
-			}
-		}
-
-		/* PCIe Root Port 2 and 6 */
-		Case (Package() { 2, 6 }) {
-			If (PICM) {
-				Return (IQBA)
-			} Else {
-				Return (IQBP)
-			}
-		}
-
-		/* PCIe Root Port 3 and 7 */
-		Case (Package() { 3, 7 }) {
-			If (PICM) {
-				Return (IQCA)
-			} Else {
-				Return (IQCP)
-			}
-		}
-
-		/* PCIe Root Port 4 and 8 */
-		Case (Package() { 4, 8 }) {
-			If (PICM) {
-				Return (IQDA)
-			} Else {
-				Return (IQDP)
-			}
-		}
-
-		Default {
-			If (PICM) {
-				Return (IQDA)
-			} Else {
-				Return (IQDP)
-			}
-		}
-	}
-}
-
-Device (RP01)
-{
-	Name (_ADR, 0x001c0000)
-
-	#include "pcie_port.asl"
-
-	Method (_PRT)
-	{
-		Return (IRQM (RPPN))
-	}
-}
-
-Device (RP02)
-{
-	Name (_ADR, 0x001c0001)
-
-	#include "pcie_port.asl"
-
-	Method (_PRT)
-	{
-		Return (IRQM (RPPN))
-	}
-}
-
-Device (RP03)
-{
-	Name (_ADR, 0x001c0002)
-
-	#include "pcie_port.asl"
-
-	Method (_PRT)
-	{
-		Return (IRQM (RPPN))
-	}
-}
-
-Device (RP04)
-{
-	Name (_ADR, 0x001c0003)
-
-	#include "pcie_port.asl"
-
-	Method (_PRT)
-	{
-		Return (IRQM (RPPN))
-	}
-}
-
-Device (RP05)
-{
-	Name (_ADR, 0x001c0004)
-
-	#include "pcie_port.asl"
-
-	Method (_PRT)
-	{
-		Return (IRQM (RPPN))
-	}
-}
-
-Device (RP06)
-{
-	Name (_ADR, 0x001c0005)
-
-	#include "pcie_port.asl"
-
-	Method (_PRT)
-	{
-		Return (IRQM (RPPN))
-	}
-}
-
-Device (RP07)
-{
-	Name (_ADR, 0x001c0006)
-
-	#include "pcie_port.asl"
-
-	Method (_PRT)
-	{
-		Return (IRQM (RPPN))
-	}
-}
-
-Device (RP08)
-{
-	Name (_ADR, 0x001c0007)
-
-	#include "pcie_port.asl"
-
-	Method (_PRT)
-	{
-		Return (IRQM (RPPN))
-	}
-}
diff --git a/src/soc/intel/broadwell/acpi/pcie_port.asl b/src/soc/intel/broadwell/acpi/pcie_port.asl
deleted file mode 100644
index d48ecd036e..0000000000
--- a/src/soc/intel/broadwell/acpi/pcie_port.asl
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Included in each PCIe Root Port device */
-
-OperationRegion (RPCS, PCI_Config, 0x00, 0xFF)
-Field (RPCS, AnyAcc, NoLock, Preserve)
-{
-	Offset (0x4c),	// Link Capabilities
-	, 24,
-	RPPN, 8,	// Root Port Number
-}
diff --git a/src/soc/intel/broadwell/acpi/sata.asl b/src/soc/intel/broadwell/acpi/sata.asl
deleted file mode 100644
index cdb6e523a9..0000000000
--- a/src/soc/intel/broadwell/acpi/sata.asl
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-// Intel SATA Controller 0:1f.2
-Device (SATA)
-{
-	Name (_ADR, 0x001f0002)
-}
diff --git a/src/soc/intel/broadwell/acpi/serialio.asl b/src/soc/intel/broadwell/acpi/serialio.asl
deleted file mode 100644
index 218ddc3b40..0000000000
--- a/src/soc/intel/broadwell/acpi/serialio.asl
+++ /dev/null
@@ -1,616 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-// Intel Serial IO Devices in ACPI Mode
-
-// Serial IO Device BAR0 and BAR1 is 4KB
-#define SIO_BAR_LEN 0x1000
-
-// Put SerialIO device in D0 state
-// Arg0 - BAR1 of device
-// Arg1 - Set if device is in ACPI mode
-Method (LPD0, 2, Serialized)
-{
-	// PCI mode devices will be handled by OS PCI bus driver
-	If (LEqual (Arg1, 0)) {
-		Return
-	}
-
-	OperationRegion (SPRT, SystemMemory, Add (Arg0, 0x84), 4)
-	Field (SPRT, DWordAcc, NoLock, Preserve)
-	{
-		SPCS, 32
-	}
-
-	And (SPCS, 0xFFFFFFFC, SPCS)
-	Store (SPCS, Local0) // Read back after writing
-
-	// Use Local0 to avoid iasl warning: Method Local is set but never used
-	And(Local0, Ones, Local0)
-}
-
-// Put SerialIO device in D3 state
-// Arg0 - BAR1 of device
-// Arg1 - Set if device is in ACPI mode
-Method (LPD3, 2, Serialized)
-{
-	// PCI mode devices will be handled by OS PCI bus driver
-	If (LEqual (Arg1, 0)) {
-		Return
-	}
-
-	OperationRegion (SPRT, SystemMemory, Add (Arg0, 0x84), 4)
-	Field (SPRT, DWordAcc, NoLock, Preserve)
-	{
-		SPCS, 32
-	}
-
-	Or (SPCS, 0x3, SPCS)
-	Store (SPCS, Local0) // Read back after writing
-
-	// Use Local0 to avoid iasl warning: Method Local is set but never used
-	And(Local0, Ones, Local0)
-}
-
-// Serial IO Resource Consumption for BAR1
-Device (SIOR)
-{
-	Name (_HID, EISAID("PNP0C02"))
-	Name (_UID, 4)
-
-	Name (RBUF, ResourceTemplate()
-	{
-		// Serial IO BAR1 (PCI config space) resources
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D0) // SDMA
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D1) // I2C0
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D2) // I2C1
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D3) // SPI0
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D4) // SPI1
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D5) // UART0
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D6) // UART1
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D7) // SDIO
-	})
-
-	// Update BAR1 address and length if set in NVS
-	Method (_CRS, 0, NotSerialized)
-	{
-		// SDMA
-		If (LNotEqual (\S0B1, Zero)) {
-			CreateDwordField (^RBUF, ^B1D0._BAS, B0AD)
-			CreateDwordField (^RBUF, ^B1D0._LEN, B0LN)
-			Store (\S0B1, B0AD)
-			Store (SIO_BAR_LEN, B0LN)
-		}
-
-		// I2C0
-		If (LNotEqual (\S1B1, Zero)) {
-			CreateDwordField (^RBUF, ^B1D1._BAS, B1AD)
-			CreateDwordField (^RBUF, ^B1D1._LEN, B1LN)
-			Store (\S1B1, B1AD)
-			Store (SIO_BAR_LEN, B1LN)
-		}
-
-		// I2C1
-		If (LNotEqual (\S2B1, Zero)) {
-			CreateDwordField (^RBUF, ^B1D2._BAS, B2AD)
-			CreateDwordField (^RBUF, ^B1D2._LEN, B2LN)
-			Store (\S2B1, B2AD)
-			Store (SIO_BAR_LEN, B2LN)
-		}
-
-		// SPI0
-		If (LNotEqual (\S3B1, Zero)) {
-			CreateDwordField (^RBUF, ^B1D3._BAS, B3AD)
-			CreateDwordField (^RBUF, ^B1D3._LEN, B3LN)
-			Store (\S3B1, B3AD)
-			Store (SIO_BAR_LEN, B3LN)
-		}
-
-		// SPI1
-		If (LNotEqual (\S4B1, Zero)) {
-			CreateDwordField (^RBUF, ^B1D4._BAS, B4AD)
-			CreateDwordField (^RBUF, ^B1D4._LEN, B4LN)
-			Store (\S4B1, B4AD)
-			Store (SIO_BAR_LEN, B4LN)
-		}
-
-		// UART0
-		If (LNotEqual (\S5B1, Zero)) {
-			CreateDwordField (^RBUF, ^B1D5._BAS, B5AD)
-			CreateDwordField (^RBUF, ^B1D5._LEN, B5LN)
-			Store (\S5B1, B5AD)
-			Store (SIO_BAR_LEN, B5LN)
-		}
-
-		// UART1
-		If (LNotEqual (\S6B1, Zero)) {
-			CreateDwordField (^RBUF, ^B1D6._BAS, B6AD)
-			CreateDwordField (^RBUF, ^B1D6._LEN, B6LN)
-			Store (\S6B1, B6AD)
-			Store (SIO_BAR_LEN, B6LN)
-		}
-
-		// SDIO
-		If (LNotEqual (\S7B1, Zero)) {
-			CreateDwordField (^RBUF, ^B1D7._BAS, B7AD)
-			CreateDwordField (^RBUF, ^B1D7._LEN, B7LN)
-			Store (\S7B1, B7AD)
-			Store (SIO_BAR_LEN, B7LN)
-		}
-
-		Return (RBUF)
-	}
-}
-
-Device (SDMA)
-{
-	// Serial IO DMA Controller
-	Name (_HID, "INTL9C60")
-	Name (_UID, 1)
-	Name (_ADR, 0x00150000)
-
-	// BAR0 is assigned during PCI enumeration and saved into NVS
-	Name (RBUF, ResourceTemplate ()
-	{
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		// Update BAR0 address and length if set in NVS
-		If (LNotEqual (\S0B0, Zero)) {
-			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
-			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
-			Store (\S0B0, B0AD)
-			Store (SIO_BAR_LEN, B0LN)
-		}
-
-		Return (RBUF)
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		If (LEqual (\S0EN, 0)) {
-			Return (0x0)
-		} Else {
-			Return (0xF)
-		}
-	}
-}
-
-Device (I2C0)
-{
-	// Serial IO I2C0 Controller
-	Method (_HID)
-	{
-		If (\ISWP ()) {
-			// WildcatPoint
-			Return ("INT3432")
-		}
-
-		// LynxPoint-LP
-		Return ("INT33C2")
-	}
-	Name (_UID, 1)
-	Name (_ADR, 0x00150001)
-
-	Name (SSCN, Package () { 432, 507, 30 })
-	Name (FMCN, Package () { 72, 160, 30 })
-
-	// BAR0 is assigned during PCI enumeration and saved into NVS
-	Name (RBUF, ResourceTemplate ()
-	{
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
-	})
-
-	// DMA channels are only used if Serial IO DMA controller is enabled
-	Name (DBUF, ResourceTemplate ()
-	{
-		FixedDMA (0x18, 4, Width32Bit, DMA1) // Tx
-		FixedDMA (0x19, 5, Width32Bit, DMA2) // Rx
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		// Update BAR0 address and length if set in NVS
-		If (LNotEqual (\S1B0, Zero)) {
-			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
-			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
-			Store (\S1B0, B0AD)
-			Store (SIO_BAR_LEN, B0LN)
-		}
-
-		// Check if Serial IO DMA Controller is enabled
-		If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) {
-			Return (ConcatenateResTemplate (RBUF, DBUF))
-		} Else {
-			Return (RBUF)
-		}
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		If (LEqual (\S1EN, 0)) {
-			Return (0x0)
-		} Else {
-			Return (0xF)
-		}
-	}
-
-	Method (_PS0, 0, Serialized)
-	{
-		^^LPD0 (\S1B1, \S1EN)
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-		^^LPD3 (\S1B1, \S1EN)
-	}
-}
-
-Device (I2C1)
-{
-	// Serial IO I2C1 Controller
-	Method (_HID)
-	{
-		If (\ISWP ()) {
-			// WildcatPoint
-			Return ("INT3433")
-		}
-
-		// LynxPoint-LP
-		Return ("INT33C3")
-	}
-	Name (_UID, 1)
-	Name (_ADR, 0x00150002)
-
-	Name (SSCN, Package () { 432, 507, 30 })
-	Name (FMCN, Package () { 72, 160, 30 })
-
-	// BAR0 is assigned during PCI enumeration and saved into NVS
-	Name (RBUF, ResourceTemplate ()
-	{
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
-	})
-
-	// DMA channels are only used if Serial IO DMA controller is enabled
-	Name (DBUF, ResourceTemplate ()
-	{
-		FixedDMA (0x1A, 6, Width32Bit, DMA1) // Tx
-		FixedDMA (0x1B, 7, Width32Bit, DMA2) // Rx
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		// Update BAR0 address and length if set in NVS
-		If (LNotEqual (\S2B0, Zero)) {
-			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
-			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
-			Store (\S2B0, B0AD)
-			Store (SIO_BAR_LEN, B0LN)
-		}
-
-		// Check if Serial IO DMA Controller is enabled
-		If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) {
-			Return (ConcatenateResTemplate (RBUF, DBUF))
-		} Else {
-			Return (RBUF)
-		}
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		If (LEqual (\S2EN, 0)) {
-			Return (0x0)
-		} Else {
-			Return (0xF)
-		}
-	}
-
-	Method (_PS0, 0, Serialized)
-	{
-		^^LPD0 (\S2B1, \S2EN)
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-		^^LPD3 (\S2B1, \S2EN)
-	}
-}
-
-Device (SPI0)
-{
-	// Serial IO SPI0 Controller
-	Method (_HID)
-	{
-		If (\ISWP ()) {
-			// WildcatPoint
-			Return ("INT3430")
-		}
-
-		// LynxPoint-LP
-		Return ("INT33C0")
-	}
-	Name (_UID, 1)
-	Name (_ADR, 0x00150003)
-
-	// BAR0 is assigned during PCI enumeration and saved into NVS
-	Name (RBUF, ResourceTemplate ()
-	{
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		// Update BAR0 address and length if set in NVS
-		If (LNotEqual (\S3B0, Zero)) {
-			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
-			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
-			Store (\S3B0, B0AD)
-			Store (SIO_BAR_LEN, B0LN)
-		}
-
-		Return (RBUF)
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		If (LEqual (\S3EN, 0)) {
-			Return (0x0)
-		} Else {
-			Return (0xF)
-		}
-	}
-
-	Method (_PS0, 0, Serialized)
-	{
-		^^LPD0 (\S3B1, \S3EN)
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-		^^LPD3 (\S3B1, \S3EN)
-	}
-}
-
-Device (SPI1)
-{
-	// Serial IO SPI1 Controller
-	Method (_HID)
-	{
-		If (\ISWP ()) {
-			// WildcatPoint
-			Return ("INT3431")
-		}
-
-		// LynxPoint-LP
-		Return ("INT33C1")
-	}
-	Name (_UID, 1)
-	Name (_ADR, 0x00150004)
-
-	// BAR0 is assigned during PCI enumeration and saved into NVS
-	Name (RBUF, ResourceTemplate ()
-	{
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
-	})
-
-	// DMA channels are only used if Serial IO DMA controller is enabled
-	Name (DBUF, ResourceTemplate ()
-	{
-		FixedDMA (0x10, 0, Width32Bit, DMA1) // Tx
-		FixedDMA (0x11, 1, Width32Bit, DMA2) // Rx
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		// Update BAR0 address and length if set in NVS
-		If (LNotEqual (\S4B0, Zero)) {
-			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
-			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
-			Store (\S4B0, B0AD)
-			Store (SIO_BAR_LEN, B0LN)
-		}
-
-		// Check if Serial IO DMA Controller is enabled
-		If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) {
-			Return (ConcatenateResTemplate (RBUF, DBUF))
-		} Else {
-			Return (RBUF)
-		}
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		If (LEqual (\S4EN, 0)) {
-			Return (0x0)
-		} Else {
-			Return (0xF)
-		}
-	}
-
-	Method (_PS0, 0, Serialized)
-	{
-		^^LPD0 (\S4B1, \S4EN)
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-		^^LPD3 (\S4B1, \S4EN)
-	}
-}
-
-Device (UAR0)
-{
-	// Serial IO UART0 Controller
-	Method (_HID)
-	{
-		If (\ISWP ()) {
-			// WildcatPoint
-			Return ("INT3434")
-		}
-
-		// LynxPoint-LP
-		Return ("INT33C4")
-	}
-	Name (_UID, 1)
-	Name (_ADR, 0x00150005)
-
-	// BAR0 is assigned during PCI enumeration and saved into NVS
-	Name (RBUF, ResourceTemplate ()
-	{
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {13}
-	})
-
-	// DMA channels are only used if Serial IO DMA controller is enabled
-	Name (DBUF, ResourceTemplate ()
-	{
-		FixedDMA (0x16, 2, Width32Bit, DMA1) // Tx
-		FixedDMA (0x17, 3, Width32Bit, DMA2) // Rx
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		// Update BAR0 address and length if set in NVS
-		If (LNotEqual (\S5B0, Zero)) {
-			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
-			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
-			Store (\S5B0, B0AD)
-			Store (SIO_BAR_LEN, B0LN)
-		}
-
-		// Check if Serial IO DMA Controller is enabled
-		If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) {
-			Return (ConcatenateResTemplate (RBUF, DBUF))
-		} Else {
-			Return (RBUF)
-		}
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		If (LEqual (\S5EN, 0)) {
-			Return (0x0)
-		} Else {
-			Return (0xF)
-		}
-	}
-
-	Method (_PS0, 0, Serialized)
-	{
-		^^LPD0 (\S5B1, \S5EN)
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-		^^LPD3 (\S5B1, \S5EN)
-	}
-}
-
-Device (UAR1)
-{
-	// Serial IO UART1 Controller
-	Method (_HID)
-	{
-		If (\ISWP ()) {
-			// WildcatPoint
-			Return ("INT3435")
-		}
-
-		// LynxPoint-LP
-		Return ("INT33C5")
-	}
-	Name (_UID, 1)
-	Name (_ADR, 0x00150006)
-
-	// BAR0 is assigned during PCI enumeration and saved into NVS
-	Name (RBUF, ResourceTemplate ()
-	{
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {13}
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		// Update BAR0 address and length if set in NVS
-		If (LNotEqual (\S6B0, Zero)) {
-			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
-			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
-			Store (\S6B0, B0AD)
-			Store (SIO_BAR_LEN, B0LN)
-		}
-
-		Return (RBUF)
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		If (LEqual (\S6EN, 0)) {
-			Return (0x0)
-		} Else {
-			Return (0xF)
-		}
-	}
-
-	Method (_PS0, 0, Serialized)
-	{
-		^^LPD0 (\S6B1, \S6EN)
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-		^^LPD3 (\S6B1, \S6EN)
-	}
-}
-
-Device (SDIO)
-{
-	// Serial IO SDIO Controller
-	Method (_HID)
-	{
-		If (\ISWP ()) {
-			// WildcatPoint
-			Return ("INT3436")
-		}
-
-		// LynxPoint-LP
-		Return ("INT33C6")
-	}
-	Name (_CID, "PNP0D40")
-	Name (_UID, 1)
-	Name (_ADR, 0x00170000)
-
-	// BAR0 is assigned during PCI enumeration and saved into NVS
-	Name (RBUF, ResourceTemplate ()
-	{
-		Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
-		Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {5}
-	})
-
-	Method (_CRS, 0, NotSerialized)
-	{
-		// Update BAR0 address and length if set in NVS
-		If (LNotEqual (\S7B0, Zero)) {
-			CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
-			CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
-			Store (\S7B0, B0AD)
-			Store (SIO_BAR_LEN, B0LN)
-		}
-
-		Return (RBUF)
-	}
-
-	Method (_STA, 0, NotSerialized)
-	{
-		If (LEqual (\S7EN, 0)) {
-			Return (0x0)
-		} Else {
-			Return (0xF)
-		}
-	}
-}
diff --git a/src/soc/intel/broadwell/acpi/smbus.asl b/src/soc/intel/broadwell/acpi/smbus.asl
deleted file mode 100644
index 32b0b9cc62..0000000000
--- a/src/soc/intel/broadwell/acpi/smbus.asl
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-// Intel SMBus Controller 0:1f.3
-
-Device (SBUS)
-{
-	Name (_ADR, 0x001f0003)
-}
diff --git a/src/soc/intel/broadwell/acpi/xhci.asl b/src/soc/intel/broadwell/acpi/xhci.asl
deleted file mode 100644
index 22e3cbceaf..0000000000
--- a/src/soc/intel/broadwell/acpi/xhci.asl
+++ /dev/null
@@ -1,375 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-// XHCI Controller 0:14.0
-
-Device (XHCI)
-{
-	Name (_ADR, 0x00140000)
-
-	Name (PLSD, 5) // Port Link State - RxDetect
-	Name (PLSP, 7) // Port Link State - Polling
-
-	OperationRegion (XPRT, PCI_Config, 0x00, 0x100)
-	Field (XPRT, AnyAcc, NoLock, Preserve)
-	{
-		Offset (0x0),
-		DVID, 16,
-		Offset (0x10),
-		, 16,
-		XMEM, 16, // MEM_BASE
-		Offset (0x40),
-		, 11,
-		SWAI, 1,
-		, 20,
-		Offset (0x44),
-		, 12,
-		SAIP, 2,
-		, 18,
-		Offset (0x74),
-		D0D3, 2,
-		, 6,
-		PMEE, 1,  // PME_EN
-		, 6,
-		PMES, 1,  // PME_STS
-		Offset (0xb0),
-		, 13,
-		MB13, 1,
-		MB14, 1,
-		Offset (0xd0),
-		PR2R, 32,  // USB2PR
-		PR2M, 32,  // USB2PRM
-		PR3R, 32,  // USB3PR
-		PR3M, 32,  // USB3PRM
-	}
-
-	// Clear status bits
-	Method (LPCL, 0, Serialized)
-	{
-		OperationRegion (XREG, SystemMemory,
-				 ShiftLeft (^XMEM, 16), 0x600)
-		Field (XREG, DWordAcc, Lock, Preserve)
-		{
-			Offset (0x510), // PORTSCNUSB3[0]
-			PSC0, 32,
-			Offset (0x520), // PORTSCNUSB3[1]
-			PSC1, 32,
-			Offset (0x530), // PORTSCNUSB3[2]
-			PSC2, 32,
-			Offset (0x540), // PORTSCNUSB3[3]
-			PSC3, 32,
-		}
-
-		// Port Enabled/Disabled (Bit 1)
-		Name (PEDB, ShiftLeft (1, 1))
-
-		// Change Status (Bits 23:17)
-		Name (CHST, ShiftLeft (0x7f, 17))
-
-		// Port 0
-		And (PSC0, Not (PEDB), Local0)
-		Or (Local0, CHST, PSC0)
-
-		// Port 1
-		And (PSC1, Not (PEDB), Local0)
-		Or (Local0, CHST, PSC1)
-
-		// Port 2
-		And (PSC2, Not (PEDB), Local0)
-		Or (Local0, CHST, PSC2)
-
-		// Port 3
-		And (PSC3, Not (PEDB), Local0)
-		Or (Local0, CHST, PSC3)
-	}
-
-	Method (LPS0, 0, Serialized)
-	{
-		OperationRegion (XREG, SystemMemory,
-				 ShiftLeft (^XMEM, 16), 0x600)
-		Field (XREG, DWordAcc, Lock, Preserve)
-		{
-			Offset (0x510), // PORTSCNUSB3
-			, 5,
-			PLS1, 4,	// [8:5] Port Link State
-			PPR1, 1,	// [9] Port Power
-			, 7,
-			CSC1, 1,	// [17] Connect Status Change
-			, 1,
-			WRC1, 1,	// [19] Warm Port Reset Change
-			, 11,
-			WPR1, 1,	// [31] Warm Port Reset
-			Offset (0x520), // PORTSCNUSB3
-			, 5,
-			PLS2, 4,	// [8:5] Port Link State
-			PPR2, 1,	// [9] Port Power
-			, 7,
-			CSC2, 1,	// [17] Connect Status Change
-			, 1,
-			WRC2, 1,	// [19] Warm Port Reset Change
-			, 11,
-			WPR2, 1,	// [31] Warm Port Reset
-			Offset (0x530), // PORTSCNUSB3
-			, 5,
-			PLS3, 4,	// [8:5] Port Link State
-			PPR3, 1,	// [9] Port Power
-			, 7,
-			CSC3, 1,	// [17] Connect Status Change
-			, 1,
-			WRC3, 1,	// [19] Warm Port Reset Change
-			, 11,
-			WPR3, 1,	// [31] Warm Port Reset
-			Offset (0x540), // PORTSCNUSB3
-			, 5,
-			PLS4, 4,	// [8:5] Port Link State
-			PPR4, 1,	// [9] Port Power
-			, 7,
-			CSC4, 1,	// [17] Connect Status Change
-			, 1,
-			WRC4, 1,	// [19] Warm Port Reset Change
-			, 11,
-			WPR4, 1,	// [31] Warm Port Reset
-		}
-
-		// Wait for all powered ports to finish polling
-		Store (10, Local0)
-		While (LOr (LOr (LAnd (LEqual (PPR1, 1), LEqual (PLS1, PLSP)),
-				 LAnd (LEqual (PPR2, 1), LEqual (PLS2, PLSP))),
-			    LOr (LAnd (LEqual (PPR3, 1), LEqual (PLS3, PLSP)),
-				 LAnd (LEqual (PPR4, 1), LEqual (PLS4, PLSP)))))
-		{
-			If (LEqual (Local0, 0)) {
-				Break
-			}
-			Decrement (Local0)
-			Stall (10)
-		}
-
-		// For each USB3 Port:
-		//   If port is disconnected (PLS=5 PP=1 CSC=0)
-		//     1) Issue warm reset (WPR=1)
-		//     2) Poll for warm reset complete (WRC=0)
-		//     3) Write 1 to port status to clear
-
-		// Local# indicate if port is reset
-		Store (0, Local1)
-		Store (0, Local2)
-		Store (0, Local3)
-		Store (0, Local4)
-
-		If (LAnd (LEqual (PLS1, PLSD),
-		          LAnd (LEqual (CSC1, 0), LEqual (PPR1, 1)))) {
-			Store (1, WPR1)	      // Issue warm reset
-			Store (1, Local1)
-		}
-		If (LAnd (LEqual (PLS2, PLSD),
-		          LAnd (LEqual (CSC2, 0), LEqual (PPR2, 1)))) {
-			Store (1, WPR2)	      // Issue warm reset
-			Store (1, Local2)
-		}
-		If (LAnd (LEqual (PLS3, PLSD),
-		          LAnd (LEqual (CSC3, 0), LEqual (PPR3, 1)))) {
-			Store (1, WPR3)	      // Issue warm reset
-			Store (1, Local3)
-		}
-		If (LAnd (LEqual (PLS4, PLSD),
-		          LAnd (LEqual (CSC4, 0), LEqual (PPR4, 1)))) {
-			Store (1, WPR4)	      // Issue warm reset
-			Store (1, Local4)
-		}
-
-		// Poll for warm reset complete on all ports that were reset
-		Store (10, Local0)
-		While (LOr (LOr (LAnd (LEqual (Local1, 1), LEqual (WRC1, 0)),
-				 LAnd (LEqual (Local2, 1), LEqual (WRC2, 0))),
-			    LOr (LAnd (LEqual (Local3, 1), LEqual (WRC3, 0)),
-			         LAnd (LEqual (Local4, 1), LEqual (WRC4, 0)))))
-		{
-			If (LEqual (Local0, 0)) {
-				Break
-			}
-			Decrement (Local0)
-			Stall (10)
-		}
-
-		// Clear status bits in all ports
-		LPCL ()
-	}
-
-	Method (_PSC, 0, NotSerialized)
-	{
-		Return (^D0D3)
-	}
-
-	Method (_PS0, 0, Serialized)
-	{
-		If (LEqual (^DVID, 0xFFFF)) {
-			Return ()
-		}
-		If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) {
-			Return ()
-		}
-
-		OperationRegion (XREG, SystemMemory,
-				 Add (ShiftLeft (^XMEM, 16), 0x8000), 0x200)
-		Field (XREG, DWordAcc, Lock, Preserve)
-		{
-			Offset (0x0e0), // AUX Reset Control 1
-			, 15,
-			AX15, 1,
-			Offset (0x154), // AUX Domain PM Control Register 2
-			, 31,
-			CLK2, 1,
-			Offset (0x16c), // AUX Clock Control
-			, 2,
-			CLK0, 1,
-			, 11,
-			CLK1, 1, // USB3 Port Aux/Core Clock Gating Enable
-		}
-
-		// If device is in D3, set back to D0
-		Store (^D0D3, Local0)
-		if (LEqual (Local0, 3)) {
-			Store (0, ^D0D3)
-		}
-
-		if (LNot (\ISWP())) {
-			// Clear PCI 0xB0[14:13]
-			Store (0, ^MB13)
-			Store (0, ^MB14)
-
-			// Clear MMIO 0x816C[14,2]
-			Store (0, CLK0)
-			Store (0, CLK1)
-
-			// Set MMIO 0x8154[31]
-			Store (1, CLK2)
-
-			// Handle per-port reset if needed
-			LPS0 ()
-
-			// Set MMIO 0x80e0[15]
-			Store (1, AX15)
-
-			// Clear PCI CFG offset 0x40[11]
-			Store (0, ^SWAI)
-
-			// Clear PCI CFG offset 0x44[13:12]
-			Store (0, ^SAIP)
-		}
-
-		Return ()
-	}
-
-	Method (_PS3, 0, Serialized)
-	{
-		If (LEqual (^DVID, 0xFFFF)) {
-			Return ()
-		}
-		If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) {
-			Return ()
-		}
-
-		OperationRegion (XREG, SystemMemory,
-				 Add (ShiftLeft (^XMEM, 16), 0x8000), 0x200)
-		Field (XREG, DWordAcc, Lock, Preserve)
-		{
-			Offset (0x0e0), // AUX Reset Control 1
-			, 15,
-			AX15, 1,
-			Offset (0x154), // AUX Domain PM Control Register 2
-			, 31,
-			CLK2, 1,
-			Offset (0x16c), // AUX Clock Control
-			, 2,
-			CLK0, 1,
-			, 11,
-			CLK1, 1, // USB3 Port Aux/Core Clock Gating Enable
-		}
-
-		Store (1, ^PMES) // Clear PME Status
-		Store (1, ^PMEE) // Enable PME
-
-		// If device is in D3, set back to D0
-		Store (^D0D3, Local0)
-		if (LEqual (Local0, 3)) {
-			Store (0, ^D0D3)
-		}
-
-		if (LNot (\ISWP())) {
-			// Set PCI 0xB0[14:13]
-			Store (1, ^MB13)
-			Store (1, ^MB14)
-
-			// Set MMIO 0x816C[14,2]
-			Store (1, CLK0)
-			Store (1, CLK1)
-
-			// Clear MMIO 0x8154[31]
-			Store (0, CLK2)
-
-			// Clear MMIO 0x80e0[15]
-			Store (0, AX15)
-
-			// Set PCI CFG offset 0x40[11]
-			Store (1, ^SWAI)
-
-			// Set PCI CFG offset 0x44[13:12]
-			Store (1, ^SAIP)
-		}
-
-		// Put device in D3
-		Store (3, ^D0D3)
-
-		Return ()
-	}
-
-	Name (_PRW, Package(){ 0x6d, 3 })
-
-	// Leave USB ports on for to allow Wake from USB
-
-	Method(_S3D,0)	// Highest D State in S3 State
-	{
-		Return (3)
-	}
-
-	Method(_S4D,0)	// Highest D State in S4 State
-	{
-		Return (3)
-	}
-
-	Device (HUB7)
-	{
-		Name (_ADR, 0x00000000)
-
-		// GPLD: Generate Port Location Data (PLD)
-		Method (GPLD, 1, Serialized) {
-			Name (PCKG, Package (0x01) {
-				Buffer (0x10) {}
-			})
-
-			// REV: Revision 0x02 for ACPI 5.0
-			CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV)
-			Store (0x02, REV)
-
-			// VISI: Port visibility to user per port
-			CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI)
-			Store (Arg0, VISI)
-			Return (PCKG)
-		}
-
-		Device (PRT1) { Name (_ADR, 1) } // USB Port 0
-		Device (PRT2) { Name (_ADR, 2) } // USB Port 1
-		Device (PRT3) { Name (_ADR, 3) } // USB Port 2
-		Device (PRT4) { Name (_ADR, 4) } // USB Port 3
-		Device (PRT5) { Name (_ADR, 5) } // USB Port 4
-		Device (PRT6) { Name (_ADR, 6) } // USB Port 5
-		Device (PRT7) { Name (_ADR, 7) } // USB Port 6
-		Device (PRT8) { Name (_ADR, 8) } // USB Port 7
-		Device (SSP1) { Name (_ADR, 10) } // USB Port 10
-		Device (SSP2) { Name (_ADR, 11) } // USB Port 11
-		Device (SSP3) { Name (_ADR, 12) } // USB Port 12
-		Device (SSP4) { Name (_ADR, 13) } // USB Port 13
-		Device (SSP5) { Name (_ADR, 14) } // USB Port 14
-		Device (SSP6) { Name (_ADR, 15) } // USB Port 15
-	}
-}