diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2014-12-12 10:52:34 -0800 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-04-15 21:46:07 +0200 |
| commit | ab1e96a099c5197419308ed40d4fd06507b46ec2 (patch) | |
| tree | 7cf1740a87a8ce22954fe75c1c003986b900473a /src/soc/intel/broadwell/acpi | |
| parent | cb12f65931aa0bbc30c0e578c988452be70714ed (diff) | |
broadwell: Fixes for _SWS support
- These should be 64bit values so when they try to return -1
it is interpreted properly by the kernel.
- The GPE value needs to be reset at the start so it does not
return stale data from a previous resume.
- If a GPE register is zero the value should only be updated
if it has not yet found a set bit.
BUG=chrome-os-partner:34532
BRANCH=samus,auron
TEST=build and boot on samus, suspend/resume with various
wake sources and ensure the reported _SWS values are correct
in every case.
Original-Change-Id: Ic6897f20ad2f321f3566694c032b75a3db120556
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/235012
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit be3c79b87b81563f744eb885708a52730debaccb)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I801c6e4f90dde0f5f69685f987a9831ee5e99e4a
Reviewed-on: http://review.coreboot.org/9699
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/broadwell/acpi')
| -rw-r--r-- | src/soc/intel/broadwell/acpi/globalnvs.asl | 19 |
1 files changed, 9 insertions, 10 deletions
diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/acpi/globalnvs.asl index 9bddbc212c..223d21a676 100644 --- a/src/soc/intel/broadwell/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/acpi/globalnvs.asl @@ -53,16 +53,15 @@ Field (GNVS, ByteAcc, NoLock, Preserve) TCRT, 8, // 0x10 - Critical Threshold TPSV, 8, // 0x11 - Passive Threshold TMAX, 8, // 0x12 - CPU Tj_max - , 8, // 0x13 - Unused - S5U0, 8, // 0x14 - Enable USB in S5 - S3U0, 8, // 0x15 - Enable USB in S3 - S33G, 8, // 0x16 - Enable 3G in S3 - LIDS, 8, // 0x17 - LID State - PWRS, 8, // 0x18 - AC Power State - CMEM, 32, // 0x19 - 0x1c - CBMEM TOC - CBMC, 32, // 0x1d - 0x20 - Coreboot Memory Console - PM1I, 32, // 0x21 - 0x24 - PM1 wake status bit - GPEI, 32, // 0x25 - 0x28 - GPE wake status bit + S5U0, 8, // 0x13 - Enable USB in S5 + S3U0, 8, // 0x14 - Enable USB in S3 + S33G, 8, // 0x15 - Enable 3G in S3 + LIDS, 8, // 0x16 - LID State + PWRS, 8, // 0x17 - AC Power State + CMEM, 32, // 0x18 - 0x1b - CBMEM TOC + CBMC, 32, // 0x1c - 0x1f - Coreboot Memory Console + PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit + GPEI, 64, // 0x28 - 0x2f - GPE wake status bit /* ChromeOS specific */ Offset (0x100), |