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authorAngel Pons <th3fanbus@gmail.com>2020-10-25 13:11:46 +0100
committerAngel Pons <th3fanbus@gmail.com>2020-11-04 22:03:18 +0000
commit0d8924d880ff22d074d760925413bc4ddfb6cd82 (patch)
tree1369dca7bfafb4cc26456e473e23093e29a0a80b /src/soc/intel/broadwell/acpi/systemagent.asl
parentf239b5a9f35faac861c8efd28d32c458e45cc890 (diff)
soc/intel/broadwell: Align ACPI with Haswell/Lynxpoint
Drop unnecessary smbus.asl in favor of southbridge common code. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 does not change. Change-Id: I13b35d2155a2cede0a56846b8bf8a79d4ebfc7b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46757 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/broadwell/acpi/systemagent.asl')
-rw-r--r--src/soc/intel/broadwell/acpi/systemagent.asl8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/broadwell/acpi/systemagent.asl b/src/soc/intel/broadwell/acpi/systemagent.asl
index 258e6e7e7a..3e7ced0296 100644
--- a/src/soc/intel/broadwell/acpi/systemagent.asl
+++ b/src/soc/intel/broadwell/acpi/systemagent.asl
@@ -141,9 +141,9 @@ Name (MCRS, ResourceTemplate()
Method (_CRS, 0, Serialized)
{
// Find PCI resource area in MCRS
- CreateDwordField(MCRS, ^PM01._MIN, PMIN)
- CreateDwordField(MCRS, ^PM01._MAX, PMAX)
- CreateDwordField(MCRS, ^PM01._LEN, PLEN)
+ CreateDwordField (MCRS, ^PM01._MIN, PMIN)
+ CreateDwordField (MCRS, ^PM01._MAX, PMAX)
+ CreateDwordField (MCRS, ^PM01._LEN, PLEN)
// Fix up PCI memory region
// Start with Top of Lower Usable DRAM
@@ -170,7 +170,7 @@ Method (_CRS, 0, Serialized)
/* PCI Device Resource Consumption */
Device (PDRC)
{
- Name (_HID, EISAID("PNP0C02"))
+ Name (_HID, EISAID ("PNP0C02"))
Name (_UID, 1)
Name (PDRS, ResourceTemplate() {