soc/intel/broadwell: Generate ACPI DMAR table

If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the
GFXVTBAR is only generated if the IGD is enabled.

Change-Id: Id7c899954f1bae9d2b48532ca5ee271944f0c5f6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>

1 files changed, 57 insertions, 0 deletions

diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c
index a23c8e2f4d..69c1eb81dc 100644
--- a/src/soc/intel/broadwell/acpi.c
+++ b/src/soc/intel/broadwell/acpi.c
@@ -37,6 +37,7 @@
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
+#include <soc/systemagent.h>
 #include <soc/intel/broadwell/chip.h>
 
 /*
@@ -571,6 +572,62 @@ void generate_cpu_entries(device_t device)
 	}
 }
 
+static unsigned long acpi_fill_dmar(unsigned long current)
+{
+	struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD);
+	const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff;
+	const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff;
+	const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1;
+	const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1;
+
+	/* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */
+	if (igfx_dev && igfx_dev->enabled && gfxvtbar
+			&& gfxvten && !MCHBAR32(GFXVTBAR + 4)) {
+		const unsigned long tmp = current;
+
+		current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
+		current += acpi_create_dmar_drhd_ds_pci(current, 0, 2, 0);
+
+		acpi_dmar_drhd_fixup(tmp, current);
+	}
+
+	/* VTVC0BAR has to be set, enabled, and in 32-bit space */
+	if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) {
+		const unsigned long tmp = current;
+		current += acpi_create_dmar_drhd(current,
+				DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
+		current += acpi_create_dmar_drhd_ds_ioapic(current,
+				2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0);
+		size_t i;
+		for (i = 0; i < 8; ++i)
+			current += acpi_create_dmar_drhd_ds_msi_hpet(current,
+					0, PCH_HPET_PCI_BUS,
+					PCH_HPET_PCI_SLOT, i);
+		acpi_dmar_drhd_fixup(tmp, current);
+	}
+
+	return current;
+}
+
+unsigned long northbridge_write_acpi_tables(struct device *const dev,
+					    unsigned long current,
+					    struct acpi_rsdp *const rsdp)
+{
+	/* Create DMAR table only if we have VT-d capability. */
+	const u32 capid0_a = pci_read_config32(dev, CAPID0_A);
+	if (capid0_a & VTD_DISABLE)
+		return current;
+
+	acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
+	printk(BIOS_DEBUG, "ACPI:    * DMAR\n");
+	acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar);
+	current += dmar->header.length;
+	current = acpi_align_current(current);
+	acpi_add_table(rsdp, dmar);
+
+	return current;
+}
+
 unsigned long acpi_madt_irq_overrides(unsigned long current)
 {
 	int sci = acpi_sci_irq();