soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK

This puts the cache-as-ram init in the bootblock.
Before setting up cache as ram the microcode updates are applied.

This removes the possibility for a normal/fallback setup although
implementing this should be quite easy.

Setting up LPC in the bootblock to output console on SuperIOs is not
done in this patch, therefore BOOTBLOCK_CONSOLE is not yet selected.

Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

1 files changed, 8 insertions, 0 deletions

diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index 1caf67adf4..eab8b37ba2 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -9,6 +9,13 @@ subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
 subdirs-y += ../../../cpu/intel/common
 
+bootblock-y += bootblock/cpu.c
+bootblock-y += bootblock/pch.c
+bootblock-y += bootblock/systemagent.c
+bootblock-y += ../../../cpu/intel/car/bootblock.c
+bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S
+bootblock-y += ../../../cpu/x86/early_reset.S
+
 ramstage-y += acpi.c
 ramstage-y += adsp.c
 ramstage-y += chip.c
@@ -58,6 +65,7 @@ ramstage-y += stage_cache.c
 romstage-y += stage_cache.c
 postcar-y += stage_cache.c
 ramstage-y += systemagent.c
+bootblock-y += tsc_freq.c
 ramstage-y += tsc_freq.c
 romstage-y += tsc_freq.c
 smm-y      += tsc_freq.c