diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-09-27 12:59:26 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-11-01 16:01:16 +0000 |
| commit | fbca40c9cc127487e73a602bd2332bca866cdbdb (patch) | |
| tree | 1c3e2022bf702893dea6d307d5b270d95a45bb7b /src/soc/intel/braswell | |
| parent | 083aa9ecf766fddd27e53f9476ca817ea1a2034b (diff) | |
soc/intel/braswell/chip.h: Use `bool` type
Use `bool` type where applicable.
Change-Id: I4d5422c16381676738b8614e8e50737b59739921
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/soc/intel/braswell')
| -rw-r--r-- | src/soc/intel/braswell/chip.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 732d73b64f..d493ad1688 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -8,11 +8,11 @@ #ifndef _SOC_CHIP_H_ #define _SOC_CHIP_H_ -#include <stdint.h> #include <drivers/intel/gma/i915.h> #include <fsp/util.h> #include <intelblocks/lpc_lib.h> #include <soc/pci_devs.h> +#include <types.h> #define SVID_CONFIG1 1 #define SVID_CONFIG3 3 @@ -40,12 +40,12 @@ enum usb_comp_bg_value { }; struct soc_intel_braswell_config { - uint8_t enable_xdp_tap; + bool enable_xdp_tap; enum serirq_mode serirq_mode; /* Disable SLP_X stretching after SUS power well loss */ - int disable_slp_x_stretch_sus_fail; + bool disable_slp_x_stretch_sus_fail; /* LPE Audio Clock configuration */ enum lpe_clk_src lpe_codec_clk_src; /* Both are 19.2MHz */ @@ -55,13 +55,13 @@ struct soc_intel_braswell_config { uint32_t sdcard_cap_high; /* Enable devices in ACPI mode */ - int lpss_acpi_mode; - int emmc_acpi_mode; - int sd_acpi_mode; - int lpe_acpi_mode; + bool lpss_acpi_mode; + bool emmc_acpi_mode; + bool sd_acpi_mode; + bool lpe_acpi_mode; /* Allow PCIe devices to wake system from suspend */ - int pcie_wake_enable; + bool pcie_wake_enable; /* Program USB2_COMPBG register. * [10:7] - select vref to AFE port |