diff options
| author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2015-09-09 14:12:16 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-28 20:43:22 +0100 |
| commit | d077b58c61896c71218a90292bbcd5063c11698f (patch) | |
| tree | 0d23442914cc3d1bcafae641d101f3683d9c3778 /src/soc/intel/braswell | |
| parent | 9657f3bb097ef5506d66a999118a4157ddadf7d5 (diff) | |
soc/braswell: Fix issues found during static code analysis
TEST=Build, boot to OS
Original-Reviewed-on: https://chromium-review.googlesource.com/299483
Original-Reviewed-by: Aaron Durbin <adurbin@google.com>
Change-Id: I738003b8dfff6a5255085d39e378e18d6ad36bcf
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/12738
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/braswell')
| -rw-r--r-- | src/soc/intel/braswell/chip.c | 11 | ||||
| -rw-r--r-- | src/soc/intel/braswell/pmutil.c | 13 | ||||
| -rw-r--r-- | src/soc/intel/braswell/romstage/romstage.c | 8 |
3 files changed, 22 insertions, 10 deletions
diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index f177a30eb0..57590c2ba9 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -84,7 +84,16 @@ static void enable_dev(device_t dev) void soc_silicon_init_params(SILICON_INIT_UPD *params) { device_t dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); - struct soc_intel_braswell_config *config = dev->chip_info; + struct soc_intel_braswell_config *config; + + if (!dev) { + printk(BIOS_ERR, + "Error! Device (%s) not found, " + "soc_silicon_init_params!\n", dev_path(dev)); + return; + } + + config = dev->chip_info; /* Set the parameters for SiliconInit */ printk(BIOS_DEBUG, "Updating UPD values for SiliconInit\n"); diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index 46115108ff..018915c92b 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -68,11 +68,6 @@ static void print_num_status_bits(int num_bits, uint32_t status, } } -static void print_status_bits(uint32_t status, const char * const bit_names[]) -{ - print_num_status_bits(32, status, bit_names); -} - static uint32_t print_smi_status(uint32_t smi_sts) { static const char * const smi_sts_bits[] = { @@ -99,7 +94,7 @@ static uint32_t print_smi_status(uint32_t smi_sts) return 0; printk(BIOS_DEBUG, "SMI_STS: "); - print_status_bits(smi_sts, smi_sts_bits); + print_num_status_bits(30, smi_sts, smi_sts_bits); printk(BIOS_DEBUG, "\n"); return smi_sts; @@ -175,7 +170,7 @@ static uint16_t print_pm1_status(uint16_t pm1_sts) return 0; printk(BIOS_SPEW, "PM1_STS: "); - print_status_bits(pm1_sts, pm1_sts_bits); + print_num_status_bits(16, pm1_sts, pm1_sts_bits); printk(BIOS_SPEW, "\n"); return pm1_sts; @@ -202,7 +197,7 @@ static uint32_t print_tco_status(uint32_t tco_sts) return 0; printk(BIOS_DEBUG, "TCO_STS: "); - print_status_bits(tco_sts, tco_sts_bits); + print_num_status_bits(18, tco_sts, tco_sts_bits); printk(BIOS_DEBUG, "\n"); return tco_sts; @@ -289,7 +284,7 @@ static uint32_t print_gpe_sts(uint32_t gpe_sts) return gpe_sts; printk(BIOS_DEBUG, "GPE0a_STS: "); - print_status_bits(gpe_sts, gpe_sts_bits); + print_num_status_bits(32, gpe_sts, gpe_sts_bits); printk(BIOS_DEBUG, "\n"); return gpe_sts; diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 028469a2ca..5f2a1cefcf 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -200,6 +200,14 @@ void soc_memory_init_params(struct romstage_params *params, /* Set the parameters for MemoryInit */ dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + + if (!dev) { + printk(BIOS_ERR, + "Error! Device (PCI:0:%02x.%01x) not found, " + "soc_memory_init_params!\n", LPC_DEV, LPC_FUNC); + return; + } + config = dev->chip_info; printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n"); upd->PcdMrcInitTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? |