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authorJoel Kitching <kitching@google.com>2018-08-17 15:38:59 +0800
committerMartin Roth <martinroth@google.com>2018-08-22 15:33:50 +0000
commit44cff7a8975b2adbf2866718ec8c61ab0d9bd505 (patch)
tree92d4975db05b7dde5b861f03e5ee3c65bbb6b661 /src/soc/intel/braswell
parent5846d5727a05e395d13317daba049e0e56e15d33 (diff)
cbtable: remove chromeos_acpi from cbtable
Since we can derive chromeos_acpi's location from that of ACPI GNVS, remove chromeos_acpi entry from cbtable and instead use acpi_gnvs + GVNS_CHROMEOS_ACPI_OFFSET. BUG=b:112288216 TEST=None CQ-DEPEND=CL:1179725 Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/28190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/braswell')
-rw-r--r--src/soc/intel/braswell/include/soc/device_nvs.h3
-rw-r--r--src/soc/intel/braswell/include/soc/nvs.h2
2 files changed, 1 insertions, 4 deletions
diff --git a/src/soc/intel/braswell/include/soc/device_nvs.h b/src/soc/intel/braswell/include/soc/device_nvs.h
index 268655e7cb..8ed534eb91 100644
--- a/src/soc/intel/braswell/include/soc/device_nvs.h
+++ b/src/soc/intel/braswell/include/soc/device_nvs.h
@@ -20,9 +20,6 @@
#include <stdint.h>
#include <compiler.h>
-/* Offset in Global NVS where this structure lives */
-#define DEVICE_NVS_OFFSET 0x1000
-
#define LPSS_NVS_SIO_DMA1 0
#define LPSS_NVS_I2C1 1
#define LPSS_NVS_I2C2 2
diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h
index 89a434bf8b..05831bb7d1 100644
--- a/src/soc/intel/braswell/include/soc/nvs.h
+++ b/src/soc/intel/braswell/include/soc/nvs.h
@@ -106,7 +106,7 @@ typedef struct global_nvs_t {
/* LPSS (0x1000) */
device_nvs_t dev;
} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
void acpi_create_gnvs(global_nvs_t *gnvs);
#if ENV_SMM