src/soc/intel: Drop unneeded empty lines

Change-Id: Id93aab5630e928ee4d7e957801e15a4cc8739fae
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44594
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

13 files changed, 0 insertions, 17 deletions

diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c
index 252a82ac1d..c5569a4df1 100644
--- a/src/soc/intel/braswell/bootblock/bootblock.c
+++ b/src/soc/intel/braswell/bootblock/bootblock.c
@@ -105,7 +105,6 @@ static void setup_mmconfig(void)
 	pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg);
 }
 
-
 void bootblock_soc_early_init(void)
 {
 	/* Allow memory-mapped PCI config access */
diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c
index c971cd1586..25965a04a7 100644
--- a/src/soc/intel/braswell/chip.c
+++ b/src/soc/intel/braswell/chip.c
@@ -22,7 +22,6 @@ static struct device_operations cpu_bus_ops = {
 	.init             = soc_init_cpus
 };
 
-
 static void enable_dev(struct device *dev)
 {
 	/* Set the operations if it is a special bus type */
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index bf2fe224cc..99a1f309ba 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -39,7 +39,6 @@ enum usb_comp_bg_value {
 	USB_COMP_BG_675_MV = 0,
 };
 
-
 struct soc_intel_braswell_config {
 	uint8_t enable_xdp_tap;
 	uint8_t clkreq_enable;
diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c
index 9bef5e2164..04bf1082c3 100644
--- a/src/soc/intel/braswell/cpu.c
+++ b/src/soc/intel/braswell/cpu.c
@@ -71,7 +71,6 @@ static const struct cpu_driver driver __cpu_driver = {
 	.id_table = cpu_table,
 };
 
-
 /*
  * MP and SMM loading initialization.
  */
diff --git a/src/soc/intel/braswell/gpio.c b/src/soc/intel/braswell/gpio.c
index 3195e8cdd3..854d4b5ca7 100644
--- a/src/soc/intel/braswell/gpio.c
+++ b/src/soc/intel/braswell/gpio.c
@@ -8,7 +8,6 @@
 #include <soc/pm.h>
 #include <soc/smm.h>
 
-
 #define GPIO_DEBUG
 
 /* gpio map to pad number LUTs */
@@ -29,7 +28,6 @@ static const u8 gpsecommunity_gpio_to_pad[GP_SOUTHEAST_COUNT] = {
 	66, 67, 68, 69, 75, 76, 77, 78, 79, 80,
 	81, 82, 83, 84, 85 };
 
-
 static const u8 gpswcommunity_gpio_to_pad[GP_SOUTHWEST_COUNT] = {
 	 0,  1,  2,  3,  4,  5,  6,  7, 15, 16,
 	17, 18, 19, 20, 21, 22, 30, 31, 32, 33,
@@ -156,7 +154,6 @@ static void setup_gpio_route(const struct soc_gpio_map *sw_gpios,
 	smm_southcluster_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg);
 }
 
-
 static void setup_gpios(const struct soc_gpio_map *gpios, const struct gpio_bank *community)
 {
 	const struct soc_gpio_map *config;
@@ -228,7 +225,6 @@ static void setup_gpios(const struct soc_gpio_map *gpios, const struct gpio_bank
 	write32((void *)(community->pad_base + GPIO_INTERRUPT_MASK), gpio_int_mask);
 }
 
-
 void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap)
 {
 	if (config) {
diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h
index 085104a6b6..2a01b2d346 100644
--- a/src/soc/intel/braswell/include/soc/gpio.h
+++ b/src/soc/intel/braswell/include/soc/gpio.h
@@ -69,7 +69,6 @@
 #define GP_FAMILY_CONF_REG(community, family)		\
 (COMMUNITY_BASE(community) + 0x1094 + 0x80 * family)
 
-
 /* Value written into pad control reg 0 */
 #define PAD_CONTROL_REG0_TRISTATE      (PAD_CONFIG0_DEFAULT|PAD_GPIOFG_HI_Z)
 
diff --git a/src/soc/intel/braswell/include/soc/irq.h b/src/soc/intel/braswell/include/soc/irq.h
index fcb40d52f7..0ea6335b05 100644
--- a/src/soc/intel/braswell/include/soc/irq.h
+++ b/src/soc/intel/braswell/include/soc/irq.h
@@ -126,7 +126,6 @@
 #define GPIO_S0_DED_IRQ(slot)		_GPIO_N_DED_IRQ(slot)
 #define GPIO_S5_DED_IRQ(slot)		_GPIO_E_DED_IRQ(slot)
 
-
 /* PIC IRQ settings. */
 #define PIRQ_PIC_IRQDISABLE		0x80
 #define PIRQ_PIC_IRQ3			0x3
diff --git a/src/soc/intel/braswell/lpc_init.c b/src/soc/intel/braswell/lpc_init.c
index 456b3d4a49..a69b85d25a 100644
--- a/src/soc/intel/braswell/lpc_init.c
+++ b/src/soc/intel/braswell/lpc_init.c
@@ -21,7 +21,6 @@
 #define LPC_AD3_MMIO_OFFSET	LPC_GPIO_OFFSET(50)
 #define LPC_AD1_MMIO_OFFSET	LPC_GPIO_OFFSET(52)
 
-
 /* Value written into pad control reg 0 in early init */
 #define PAD_CFG0_NATIVE(mode, term, inv_rx_tx) (PAD_GPIO_DISABLE \
 				| PAD_GPIOFG_HI_Z \
diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c
index 4ad91ae470..14be808136 100644
--- a/src/soc/intel/braswell/lpe.c
+++ b/src/soc/intel/braswell/lpe.c
@@ -102,7 +102,6 @@ static void setup_codec_clock(struct device *dev)
 	/* Default to always running. */
 	reg |= CLK_CTL_ON;
 
-
 	printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str);
 
 	clk_reg = (u32 *)(PMC_BASE_ADDRESS + PLT_CLK_CTL_0);
diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c
index cd2fc76312..4497166c6b 100644
--- a/src/soc/intel/braswell/pmutil.c
+++ b/src/soc/intel/braswell/pmutil.c
@@ -229,7 +229,6 @@ void disable_all_gpe(void)
 	disable_gpe(~0);
 }
 
-
 static uint32_t reset_gpe_status(void)
 {
 	uint16_t pmbase = get_pmbase();
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index b6b20b9e1b..a82a4abc28 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -11,7 +11,6 @@
 
 #include "../chip.h"
 
-
 static struct chipset_power_state power_state;
 
 static void migrate_power_state(int is_recovery)
@@ -83,7 +82,6 @@ int chipset_prev_sleep_state(struct chipset_power_state *ps)
 	return prev_sleep_state;
 }
 
-
 /* SOC initialization after RAM is enabled */
 void soc_after_ram_init(struct romstage_params *params)
 {
diff --git a/src/soc/intel/braswell/scc.c b/src/soc/intel/braswell/scc.c
index f56f153ce4..45ce8de982 100644
--- a/src/soc/intel/braswell/scc.c
+++ b/src/soc/intel/braswell/scc.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-
 #include <acpi/acpi_gnvs.h>
 #include <console/console.h>
 #include <device/device.h>
diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c
index d2f73bf654..6e250d81cc 100644
--- a/src/soc/intel/braswell/smihandler.c
+++ b/src/soc/intel/braswell/smihandler.c
@@ -100,7 +100,6 @@ static void tristate_gpios(uint32_t val)
 	write32((void *)COMMUNITY_GPSOUTHWEST_BASE + CFIO_140_MMIO_OFFSET, val);
 }
 
-
 static void southbridge_smi_sleep(void)
 {
 	uint32_t reg32;