diff options
| author | Brenton Dong <brenton.m.dong@intel.com> | 2016-10-18 13:57:54 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-12-21 00:11:24 +0100 |
| commit | c9b398191e5f94647b3e4e80bafb5331ae49b7c8 (patch) | |
| tree | 83c28799810ff66585bd26a9f21a0aaff6afa07e /src/soc/intel/braswell | |
| parent | 0a5971c91bac57970e3f3229b8cda735a17b3a67 (diff) | |
soc/intel/apollolake: allow ApolloLake SoC to use FSP CAR Init
FSP v2.0 Driver supports TempRamInit & TempRamExit APIs to initialize
& tear down Cache-As-Ram. Add TempRamInit & TempRamExit usage to
ApolloLake SoC when CONFIG_FSP_CAR is enabled.
Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram
is correctly set up and torn down using the FSP v2.0 APIs
without coreboot implementation of CAR init/teardown.
Change-Id: Ifd6fe8398ea147a5fb8c60076b93205bb94b1f25
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/17063
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/braswell')
0 files changed, 0 insertions, 0 deletions