diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-07-13 16:55:28 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-07-21 20:09:31 +0200 |
| commit | bbbfbf2e0fe3c1af135a955505b6a2fd73681a8e (patch) | |
| tree | 529f7c43739edd0b4400c7d9e69c7c6e4aa93569 /src/soc/intel/braswell | |
| parent | 367ddc91fffafac2c5c78df62bf34305ae11778c (diff) | |
intel fsp: remove CHIPSET_RESERVED_MEM_BYTES
FSP 1.1 platforms should be conforming to the spec. In order
to ensure following specification remove the crutch that allows
FSP to no conform.
BUG=chrome-os-partner:41961
BRANCH=None
TEST=Built.
Change-Id: I28b876773a3b6f07223d60a5133129d8f2c75bf6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c3fe08c5af41867782e422f27b0aed1b762ff34a
Original-Change-Id: Ib97027a35cdb914aca1eec0eeb225a55f51a4b4b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/285187
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/10993
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel/braswell')
| -rw-r--r-- | src/soc/intel/braswell/memmap.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/braswell/northcluster.c | 2 |
2 files changed, 1 insertions, 3 deletions
diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index 28156a360d..d1d784d73b 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -81,5 +81,5 @@ void *cbmem_top(void) */ smm_region((void **)&smm_base, &smm_size); - return (void *)(smm_base - CONFIG_CHIPSET_RESERVED_MEM_BYTES); + return (void *)smm_base; } diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index d5d7268a8f..7821a2a1ca 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -52,8 +52,6 @@ * +--------------------------+ SMMRRH, IRM0 * | TSEG | * +--------------------------+ SMMRRL - * | FSP Reserved Mem | - * +--------------------------+ SMMRRL - CONFIG_CHIPSET_RESERVED_MEM_BYTES * | Usable DRAM | * +--------------------------+ 0 * |