diff options
author | Dinesh Gehlot <digehlot@google.com> | 2023-01-17 05:06:10 +0000 |
---|---|---|
committer | Elyes Haouas <ehaouas@noos.fr> | 2023-01-18 05:19:19 +0000 |
commit | ba09eb71c8ffe94ea752cdbc83ac5f400ebc3772 (patch) | |
tree | 5bc5f89dd5b538b82a0d490204bed049d57380f8 /src/soc/intel/braswell | |
parent | 4da8830c3d4f65b2bd53ed1c0f4fd7f623ca8c1e (diff) |
soc/intel/braswell: Use common gpio.h include
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes
with the common gpio.h which includes soc/gpio.h which includes
intelblocks/gpio.h which includes soc/gpio_defs.h. This patch also fixes
alphabetic ordering of included headers.
BUG=b:261778357
TEST=Able to build and boot.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I55fa5941a9255f60c2aa23b90d16cf342d6f458f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72032
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel/braswell')
-rw-r--r-- | src/soc/intel/braswell/bootblock/bootblock.c | 2 | ||||
-rw-r--r-- | src/soc/intel/braswell/gpio.c | 4 | ||||
-rw-r--r-- | src/soc/intel/braswell/gpio_support.c | 3 | ||||
-rw-r--r-- | src/soc/intel/braswell/lpc_init.c | 4 | ||||
-rw-r--r-- | src/soc/intel/braswell/ramstage.c | 2 | ||||
-rw-r--r-- | src/soc/intel/braswell/smihandler.c | 6 |
6 files changed, 10 insertions, 11 deletions
diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index 545642f608..2c9783ad5b 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -6,8 +6,8 @@ #include <console/console.h> #include <device/pci_ops.h> #include <fsp/util.h> +#include <gpio.h> #include <pc80/mc146818rtc.h> -#include <soc/gpio.h> #include <soc/iomap.h> #include <soc/iosf.h> #include <soc/lpc.h> diff --git a/src/soc/intel/braswell/gpio.c b/src/soc/intel/braswell/gpio.c index 854d4b5ca7..58970e83c4 100644 --- a/src/soc/intel/braswell/gpio.c +++ b/src/soc/intel/braswell/gpio.c @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <arch/io.h> +#include <console/console.h> #include <device/mmio.h> #include <device/pci.h> -#include <soc/gpio.h> +#include <gpio.h> #include <soc/pm.h> #include <soc/smm.h> diff --git a/src/soc/intel/braswell/gpio_support.c b/src/soc/intel/braswell/gpio_support.c index 078ced6e55..677007d52b 100644 --- a/src/soc/intel/braswell/gpio_support.c +++ b/src/soc/intel/braswell/gpio_support.c @@ -1,9 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/mmio.h> -#include <gpio.h> #include <console/console.h> -#include <soc/gpio.h> +#include <gpio.h> /* * Return family number and internal pad number in that community by pad number diff --git a/src/soc/intel/braswell/lpc_init.c b/src/soc/intel/braswell/lpc_init.c index a69b85d25a..d476d5d6e6 100644 --- a/src/soc/intel/braswell/lpc_init.c +++ b/src/soc/intel/braswell/lpc_init.c @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/io.h> -#include <soc/gpio.h> -#include <soc/pm.h> #include <device/mmio.h> +#include <gpio.h> #include <soc/iomap.h> +#include <soc/pm.h> #define SUSPEND_CYCLE 1 #define RESUME_CYCLE 0 diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 6784eb9a5d..27a0cce87c 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -10,8 +10,8 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <fsp/util.h> +#include <gpio.h> #include <intelblocks/acpi_wake_source.h> -#include <soc/gpio.h> #include <soc/lpc.h> #include <soc/msr.h> #include <soc/pattrs.h> diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index f34eb6448f..44a66123d8 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -2,20 +2,20 @@ #include <arch/hlt.h> #include <arch/io.h> -#include <device/mmio.h> -#include <device/pci_ops.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <cpu/intel/em64t100_save_state.h> +#include <device/mmio.h> +#include <device/pci_ops.h> #include <device/pci_def.h> #include <elog.h> +#include <gpio.h> #include <soc/nvs.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <spi-generic.h> #include <stdint.h> -#include <soc/gpio.h> #include <smmstore.h> void southbridge_smi_set_eos(void) |