diff options
| author | Lee Leahy <lpleahyjr@gmail.com> | 2016-01-01 18:09:50 -0800 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-01-28 17:12:22 +0100 |
| commit | b092c9e9c1548d5c407788f24184f154e51a5e7c (patch) | |
| tree | a7b4f8850ed3f9f936c782c01767e85c69788368 /src/soc/intel/braswell | |
| parent | 98fc426a98db7e4dd5fea334edec720721d2a89c (diff) | |
drivers/intel/fsp1_1: Remove extra include references
Remove include references to the soc include directory which are not
required to build the FSP driver. Remove "duplicate" include file
definitions from file that include fsp/romstage.h. Move the definition
of fill_power_state into soc/pm.h to ensure it is still available.
TEST=Build and run on Galileo
Change-Id: Ie519b3a8da8c36b47da512d3811796eab62ce208
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13436
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/braswell')
| -rw-r--r-- | src/soc/intel/braswell/include/soc/pm.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/braswell/include/soc/romstage.h | 3 |
2 files changed, 4 insertions, 3 deletions
diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index 9708b3959e..9e527e1b78 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2015-2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -235,6 +235,8 @@ struct chipset_power_state { int prev_sleep_state; } __attribute__((packed)); +struct chipset_power_state *fill_power_state(void); + /* Power Management Utility Functions. */ uint16_t get_pmbase(void); uint32_t clear_smi_status(void); diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h index e70510bf9f..fc4f864942 100644 --- a/src/soc/intel/braswell/include/soc/romstage.h +++ b/src/soc/intel/braswell/include/soc/romstage.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2015-2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -33,7 +33,6 @@ void set_max_freq(void); /* romstage_common.c functions */ void program_base_addresses(void); -struct chipset_power_state *fill_power_state(void); int chipset_prev_sleep_state(struct chipset_power_state *ps); #endif /* _SOC_ROMSTAGE_H_ */ |