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authorKyösti Mälkki <kyosti.malkki@gmail.com>2021-01-22 08:02:50 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-01-23 20:18:29 +0000
commit540902ca47a9831d87761925b5df2699efc882a1 (patch)
tree37a885f82e233819ce86a3555ced387385847428 /src/soc/intel/braswell
parent6b43055b7a51bd3e27578bbb544aa638228f6eaf (diff)
intel/baytrail,braswell,broadwell: Add const qualifier for power_state
Change-Id: I37781c1423b49130ffd0d5f9fbdd28a36c9c6179 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/braswell')
-rw-r--r--src/soc/intel/braswell/include/soc/romstage.h2
-rw-r--r--src/soc/intel/braswell/romstage/romstage.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h
index 2cf9afa633..3f38de8f2d 100644
--- a/src/soc/intel/braswell/include/soc/romstage.h
+++ b/src/soc/intel/braswell/include/soc/romstage.h
@@ -11,7 +11,7 @@ void gfx_init(void);
void punit_init(void);
/* romstage.c functions */
-int chipset_prev_sleep_state(struct chipset_power_state *ps);
+int chipset_prev_sleep_state(const struct chipset_power_state *ps);
/* Values for FSP's PcdMemoryTypeEnable */
#define MEM_DDR3 0
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index 1738679b1e..5a1aa0ae73 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -57,7 +57,7 @@ struct chipset_power_state *fill_power_state(void)
}
/* Return 0, 3, or 5 to indicate the previous sleep state. */
-int chipset_prev_sleep_state(struct chipset_power_state *ps)
+int chipset_prev_sleep_state(const struct chipset_power_state *ps)
{
/* Default to S0. */
int prev_sleep_state = ACPI_S0;