{drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support

No C_ENVIRONMENT_BOOTBLOCK support for Braswell is available.
Enable support and add required files for the Braswell Bootblock in C.

The next changes are made support C_ENVIRONMENT_BOOTBLOCK:
- Add car_stage_entry() function bootblock-c_entry() functions.
- Specify config DCACHE_BSP_STACK_SIZE and C_ENV_BOOTBLOCK_SIZE.
- Add bootblock_c_entry().
- Move init from car_soc_XXX_console_init() to bootblock_soc_XXX_Init()

Removed the unused cache_as_ram_main() and weak car_XXX_XXX_console_init()

BUG=NA
TEST=Booting Embedded Linux on Facebook FBG-1701
     Building Google Banos

Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

7 files changed, 117 insertions, 141 deletions

diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index ed5c9728a3..920179f834 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -51,15 +51,23 @@ config CPU_SPECIFIC_OPTIONS
 	select INTEL_GMA_SWSMISCI
 	select CPU_INTEL_COMMON
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
+	select C_ENVIRONMENT_BOOTBLOCK
+
+config DCACHE_BSP_STACK_SIZE
+	hex
+	default 0x2000
+	help
+	  The amount of anticipated stack usage in CAR by bootblock and
+	  other stages.
+
+config C_ENV_BOOTBLOCK_SIZE
+	hex
+	default 0x8000
 
 config VBOOT
 	select VBOOT_MUST_REQUEST_DISPLAY
 	select VBOOT_STARTS_IN_ROMSTAGE
 
-config BOOTBLOCK_CPU_INIT
-	string
-	default "soc/intel/braswell/bootblock/bootblock.c"
-
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xe0000000
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index e479a3c5e5..1017d80c65 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -9,9 +9,14 @@ subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
 subdirs-y += ../../../cpu/intel/common
 
+bootblock-y += gpio_support.c
+bootblock-y += bootblock/bootblock.c
+bootblock-y += lpc_init.c
+bootblock-y += pmutil.c
+bootblock-y += tsc_freq.c
+
 romstage-y += gpio_support.c
 romstage-y += iosf.c
-romstage-y += lpc_init.c
 romstage-y += memmap.c
 romstage-y += pmutil.c
 romstage-y += smbus.c
diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c
index 457b8b895d..2d1a3e8687 100644
--- a/src/soc/intel/braswell/bootblock/bootblock.c
+++ b/src/soc/intel/braswell/bootblock/bootblock.c
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2013 Google, Inc.
  * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2018 Eltan B.V.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,37 +15,93 @@
  * GNU General Public License for more details.
  */
 
+#include <bootblock_common.h>
+#include <build.h>
+#include <console/console.h>
 #include <device/pci_ops.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/mtrr.h>
+#include <pc80/mc146818rtc.h>
+#include <soc/bootblock.h>
+#include <soc/gpio.h>
+#include <soc/iomap.h>
 #include <soc/iosf.h>
-#include <cpu/intel/microcode/microcode.c>
+#include <soc/lpc.h>
+#include <soc/pm.h>
+#include <soc/spi.h>
 
-static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type)
+asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 {
-	msr_t basem, maskm;
-	basem.lo = base | type;
-	basem.hi = 0;
-	wrmsr(MTRR_PHYS_BASE(reg), basem);
-	maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
-	maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
-	wrmsr(MTRR_PHYS_MASK(reg), maskm);
+	/* Call lib/bootblock.c main */
+	bootblock_main_with_timestamp(base_timestamp, NULL, 0);
 }
 
-static void enable_rom_caching(void)
+static void program_base_addresses(void)
 {
-	msr_t msr;
+	uint32_t reg;
+	const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC);
+
+	/* Memory Mapped IO registers. */
+	reg = PMC_BASE_ADDRESS | 2;
+	pci_write_config32(lpc_dev, PBASE, reg);
+	reg = IO_BASE_ADDRESS | 2;
+	pci_write_config32(lpc_dev, IOBASE, reg);
+	reg = ILB_BASE_ADDRESS | 2;
+	pci_write_config32(lpc_dev, IBASE, reg);
+	reg = SPI_BASE_ADDRESS | 2;
+	pci_write_config32(lpc_dev, SBASE, reg);
+	reg = MPHY_BASE_ADDRESS | 2;
+	pci_write_config32(lpc_dev, MPBASE, reg);
+	reg = PUNIT_BASE_ADDRESS | 2;
+	pci_write_config32(lpc_dev, PUBASE, reg);
+	reg = RCBA_BASE_ADDRESS | 1;
+	pci_write_config32(lpc_dev, RCBA, reg);
+
+	/* IO Port Registers. */
+	reg = ACPI_BASE_ADDRESS | 2;
+	pci_write_config32(lpc_dev, ABASE, reg);
+	reg = GPIO_BASE_ADDRESS | 2;
+	pci_write_config32(lpc_dev, GBASE, reg);
+}
+
+static void tco_disable(void)
+{
+	uint32_t reg;
+
+	reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT);
+	reg |= TCO_TMR_HALT;
+	outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT);
+}
+
+static void spi_init(void)
+{
+	void *scs = (void *)(SPI_BASE_ADDRESS + SCS);
+	void *bcr = (void *)(SPI_BASE_ADDRESS + BCR);
+	uint32_t reg;
+
+	/* Disable generating SMI when setting WPD bit. */
+	write32(scs, read32(scs) & ~SMIWPEN);
+	/*
+	 * Enable caching and prefetching in the SPI controller. Disable
+	 * the SMM-only BIOS write and set WPD bit.
+	 */
+	reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD;
+	reg &= ~EISS;
+	write32(bcr, reg);
+}
 
-	disable_cache();
-	/* Why only top 4MiB ? */
-	set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT);
-	enable_cache();
+static void soc_rtc_init(void)
+{
+	int rtc_failed = rtc_failure();
 
-	/* Enable Variable MTRRs */
-	msr.hi = 0x00000000;
-	msr.lo = 0x00000800;
-	wrmsr(MTRR_DEF_TYPE_MSR, msr);
+	if (rtc_failed) {
+		printk(BIOS_ERR,
+			"RTC Failure detected. Resetting date to %x/%x/%x%x\n",
+			COREBOOT_BUILD_MONTH_BCD,
+			COREBOOT_BUILD_DAY_BCD,
+			0x20,
+			COREBOOT_BUILD_YEAR_BCD);
+	}
+
+	cmos_init(rtc_failed);
 }
 
 static void setup_mmconfig(void)
@@ -67,12 +124,22 @@ static void setup_mmconfig(void)
 	pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg);
 }
 
-static void bootblock_cpu_init(void)
+
+void bootblock_soc_early_init(void)
 {
 	/* Allow memory-mapped PCI config access. */
 	setup_mmconfig();
 
-	/* Load microcode before any caching. */
-	intel_update_microcode_from_cbfs();
-	enable_rom_caching();
+	/* Early chipset initialization */
+	program_base_addresses();
+	tco_disable();
+}
+void bootblock_soc_init(void)
+{
+	/* Continue chipset initialization */
+	soc_rtc_init();
+	set_max_freq();
+	spi_init();
+
+	lpc_init();
 }
diff --git a/src/soc/intel/braswell/romstage/pmc.c b/src/soc/intel/braswell/include/soc/bootblock.h
index 127458e59c..e6e25ccbb1 100644
--- a/src/soc/intel/braswell/romstage/pmc.c
+++ b/src/soc/intel/braswell/include/soc/bootblock.h
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2015-2016 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,15 +14,9 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
-#include <soc/iomap.h>
-#include <soc/romstage.h>
+#ifndef _SOC_BOOTBLOCK_H_
+#define _SOC_BOOTBLOCK_H_
 
-void tco_disable(void)
-{
-	uint32_t reg;
+void set_max_freq(void);
 
-	reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT);
-	reg |= TCO_TMR_HALT;
-	outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT);
-}
+#endif /* _SOC_BOOTBLOCK_H_ */
diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h
index 4ecbd2c1f9..9fad9bc5a0 100644
--- a/src/soc/intel/braswell/include/soc/romstage.h
+++ b/src/soc/intel/braswell/include/soc/romstage.h
@@ -23,12 +23,10 @@
 #include <soc/pm.h>
 
 void gfx_init(void);
-void tco_disable(void);
 void punit_init(void);
 void set_max_freq(void);
 
-/* romstage_common.c functions */
-void program_base_addresses(void);
+/* romstage.c functions */
 int chipset_prev_sleep_state(struct chipset_power_state *ps);
 
 /* Values for FSP's PcdMemoryTypeEnable */
diff --git a/src/soc/intel/braswell/romstage/Makefile.inc b/src/soc/intel/braswell/romstage/Makefile.inc
index 3d3e407a29..d405133110 100644
--- a/src/soc/intel/braswell/romstage/Makefile.inc
+++ b/src/soc/intel/braswell/romstage/Makefile.inc
@@ -1,3 +1,2 @@
 romstage-y += ../../../../cpu/intel/car/romstage.c
-romstage-y += pmc.c
 romstage-y += romstage.c
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index 8dfc291d1e..e0e22f220e 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -19,90 +19,13 @@
 #include <stddef.h>
 #include <arch/io.h>
 #include <device/mmio.h>
-#include <device/pci_ops.h>
-#include <arch/cbfs.h>
-#include <cpu/x86/mtrr.h>
 #include <console/console.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <elog.h>
-#include <mrc_cache.h>
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <fsp/util.h>
-#include <soc/gpio.h>
 #include <soc/iomap.h>
 #include <soc/iosf.h>
-#include <soc/lpc.h>
-#include <soc/pci_devs.h>
 #include <soc/romstage.h>
-#include <soc/smm.h>
-#include <soc/spi.h>
-#include <build.h>
-#include <pc80/mc146818rtc.h>
 
 #include "../chip.h"
 
-void program_base_addresses(void)
-{
-	uint32_t reg;
-	const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC);
-
-	/* Memory Mapped IO registers. */
-	reg = PMC_BASE_ADDRESS | 2;
-	pci_write_config32(lpc_dev, PBASE, reg);
-	reg = IO_BASE_ADDRESS | 2;
-	pci_write_config32(lpc_dev, IOBASE, reg);
-	reg = ILB_BASE_ADDRESS | 2;
-	pci_write_config32(lpc_dev, IBASE, reg);
-	reg = SPI_BASE_ADDRESS | 2;
-	pci_write_config32(lpc_dev, SBASE, reg);
-	reg = MPHY_BASE_ADDRESS | 2;
-	pci_write_config32(lpc_dev, MPBASE, reg);
-	reg = PUNIT_BASE_ADDRESS | 2;
-	pci_write_config32(lpc_dev, PUBASE, reg);
-	reg = RCBA_BASE_ADDRESS | 1;
-	pci_write_config32(lpc_dev, RCBA, reg);
-
-	/* IO Port Registers. */
-	reg = ACPI_BASE_ADDRESS | 2;
-	pci_write_config32(lpc_dev, ABASE, reg);
-	reg = GPIO_BASE_ADDRESS | 2;
-	pci_write_config32(lpc_dev, GBASE, reg);
-}
-
-static void spi_init(void)
-{
-	void *scs = (void *)(SPI_BASE_ADDRESS + SCS);
-	void *bcr = (void *)(SPI_BASE_ADDRESS + BCR);
-	uint32_t reg;
-
-	/* Disable generating SMI when setting WPD bit. */
-	write32(scs, read32(scs) & ~SMIWPEN);
-	/*
-	 * Enable caching and prefetching in the SPI controller. Disable
-	 * the SMM-only BIOS write and set WPD bit.
-	 */
-	reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD;
-	reg &= ~EISS;
-	write32(bcr, reg);
-}
-
-static void soc_rtc_init(void)
-{
-	int rtc_failed = rtc_failure();
-
-	if (rtc_failed) {
-		printk(BIOS_ERR,
-			"RTC Failure detected. Resetting date to %x/%x/%x%x\n",
-			COREBOOT_BUILD_MONTH_BCD,
-			COREBOOT_BUILD_DAY_BCD,
-			0x20,
-			COREBOOT_BUILD_YEAR_BCD);
-	}
-
-	cmos_init(rtc_failed);
-}
 
 static struct chipset_power_state power_state;
 
@@ -171,24 +94,6 @@ int chipset_prev_sleep_state(struct chipset_power_state *ps)
 	return prev_sleep_state;
 }
 
-/* SOC initialization before the console is enabled */
-void car_soc_pre_console_init(void)
-{
-	/* Early chipset initialization */
-	program_base_addresses();
-	tco_disable();
-}
-
-/* SOC initialization after console is enabled */
-void car_soc_post_console_init(void)
-{
-	/* Continue chipset initialization */
-	soc_rtc_init();
-	set_max_freq();
-	spi_init();
-
-	lpc_init();
-}
 
 /* SOC initialization after RAM is enabled */
 void soc_after_ram_init(struct romstage_params *params)