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author | Jeremy Compostella <jeremy.compostella@intel.com> | 2023-03-13 10:55:21 -0700 |
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committer | Nick Vaccaro <nvaccaro@google.com> | 2023-03-31 20:04:43 +0000 |
commit | 11f2f88a277124713f7b0023f078fcc2e1a98c32 (patch) | |
tree | 0a5266ccb31091793d09176ac9fd4bb25a332d7e /src/soc/intel/braswell | |
parent | e7a1204f26fe3628de99b4ab4e3f32916565b95c (diff) |
mb/google/brya: Enable asynchronous End-Of-Post
Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post
right after PCI enumeration and handle the command response at
`BS_PAYLOAD_BOOT'.
With these settings we have observed a boot time reduction of about 20
to 30 ms on brya0.
BUG=b:268546941
BRANCH=firmware-brya-14505.B
TEST=Tests on brya0 with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show
End-Of-Post after PCI initialization and EOP message received at
`BS_PAYLOAD_BOOT'.
Change-Id: I81e9dc66f952c14cb14f513955d3fe853396b21c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73922
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/braswell')
0 files changed, 0 insertions, 0 deletions