diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2022-01-27 07:55:34 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-28 15:10:46 +0000 |
| commit | 0bc5d9dfff8ecd380fa914a6e0885aef04467f8d (patch) | |
| tree | fa1fc19c9f19b8e315b8d8e8fd152bd541c5a62d /src/soc/intel/braswell | |
| parent | f711bf03a694bc594a610a70251716d425fbe101 (diff) | |
src/{drivers,soc}: Fix some code indents
Change-Id: I55682de4a1bc74f170e2044de35b0d8d53ef51ff
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Diffstat (limited to 'src/soc/intel/braswell')
| -rw-r--r-- | src/soc/intel/braswell/ramstage.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 48f2193e47..42d1f9f080 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -68,11 +68,11 @@ static void fill_in_pattrs(void) dev = pcidev_on_root(LPC_DEV, LPC_FUNC); attrs->revid = pci_read_config8(dev, REVID); /* The revision to stepping IDs have two values per metal stepping. */ - if (attrs->revid >= RID_D_STEPPING_START) { + if (attrs->revid >= RID_D_STEPPING_START) { attrs->stepping = (attrs->revid - RID_D_STEPPING_START) / 2; attrs->stepping += STEP_D1; - } else if (attrs->revid >= RID_C_STEPPING_START) { + } else if (attrs->revid >= RID_C_STEPPING_START) { attrs->stepping = (attrs->revid - RID_C_STEPPING_START) / 2; attrs->stepping += STEP_C0; |