drivers/intel/gma: Move IGD OpRegion to CBMEM

It never was in GNVS, it never belonged among the ACPI tables. Having
it in CBMEM, makes it easy to look the location up on resume, and saves
us additional boilerplate.

TEST=Booted Linux on Lenovo/X201s, confirmed ASLS is set and
     intel_backlight + acpi_video synchronize, both before and
     after suspend.

Change-Id: I5fdd6634e4a671a85b1df8bc9815296ff42edf29
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40724
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 3 insertions, 113 deletions

diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c
index d0051d1fb7..a3025c23c6 100644
--- a/src/soc/intel/braswell/acpi.c
+++ b/src/soc/intel/braswell/acpi.c
@@ -460,38 +460,16 @@ unsigned long acpi_madt_irq_overrides(unsigned long current)
 	return current;
 }
 
-/* Initialize IGD OpRegion, called from ACPI code */
-static int update_igd_opregion(igd_opregion_t *opregion)
-{
-	/* FIXME: Add platform specific mailbox initialization */
-
-	return 0;
-}
-
 unsigned long southcluster_write_acpi_tables(const struct device *device, unsigned long current,
 					     struct acpi_rsdp *rsdp)
 {
 	acpi_header_t *ssdt2;
-	global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
 
 	if (!CONFIG(DISABLE_HPET)) {
 		current = acpi_write_hpet(device, current, rsdp);
 		current = acpi_align_current(current);
 	}
 
-	if (CONFIG(INTEL_GMA_ADD_VBT)) {
-		igd_opregion_t *opregion;
-
-		printk(BIOS_DEBUG, "ACPI:    * IGD OpRegion\n");
-		opregion = (igd_opregion_t *)current;
-		intel_gma_init_igd_opregion(opregion);
-		if (gnvs)
-			gnvs->aslb = (u32)opregion;
-		update_igd_opregion(opregion);
-		current += sizeof(igd_opregion_t);
-		current = acpi_align_current(current);
-	}
-
 	ssdt2 = (acpi_header_t *)current;
 	memset(ssdt2, 0, sizeof(acpi_header_t));
 	acpi_create_serialio_ssdt(ssdt2);
diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl
index c790438f65..c983d93db7 100644
--- a/src/soc/intel/braswell/acpi/globalnvs.asl
+++ b/src/soc/intel/braswell/acpi/globalnvs.asl
@@ -55,48 +55,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	TOLM,	 32,	/* 0x34 - Top of Low Memory */
 	CBMC,	 32,	/* 0x38 - coreboot mem console pointer */
 
-	/* IGD OpRegion */
-	Offset (0xb4),
-	ASLB,	32,	// 0xb4 - IGD OpRegion Base Address
-	IBTT,	 8,	// 0xb8 - IGD boot panel device
-	IPAT,	 8,	// 0xb9 - IGD panel type CMOS option
-	ITVF,	 8,	// 0xba - IGD TV format CMOS option
-	ITVM,	 8,	// 0xbb - IGD TV minor format option
-	IPSC,	 8,	// 0xbc - IGD panel scaling
-	IBLC,	 8,	// 0xbd - IGD BLC config
-	IBIA,	 8,	// 0xbe - IGD BIA config
-	ISSC,	 8,	// 0xbf - IGD SSC config
-	I409,	 8,	// 0xc0 - IGD 0409 modified settings
-	I509,	 8,	// 0xc1 - IGD 0509 modified settings
-	I609,	 8,	// 0xc2 - IGD 0609 modified settings
-	I709,	 8,	// 0xc3 - IGD 0709 modified settings
-	IDMM,	 8,	// 0xc4 - IGD Power conservation feature
-	IDMS,	 8,	// 0xc5 - IGD DVMT memory size
-	IF1E,	 8,	// 0xc6 - IGD function 1 enable
-	HVCO,	 8,	// 0xc7 - IGD HPLL VCO
-	NXD1,	32,	// 0xc8 - IGD _DGS next DID1
-	NXD2,	32,	// 0xcc - IGD _DGS next DID2
-	NXD3,	32,	// 0xd0 - IGD _DGS next DID3
-	NXD4,	32,	// 0xd4 - IGD _DGS next DID4
-	NXD5,	32,	// 0xd8 - IGD _DGS next DID5
-	NXD6,	32,	// 0xdc - IGD _DGS next DID6
-	NXD7,	32,	// 0xe0 - IGD _DGS next DID7
-	NXD8,	32,	// 0xe4 - IGD _DGS next DID8
-
-	ISCI,	 8,	// 0xe8 - IGD SMI/SCI mode (0: SCI)
-	PAVP,	 8,	// 0xe9 - IGD PAVP data
-	Offset (0xeb),
-	OSCC,	 8,	// 0xeb - PCIe OSC control
-	NPCE,	 8,	// 0xec - native PCIe support
-	PLFL,	 8,	// 0xed - platform flavor
-	BREV,	 8,	// 0xee - board revision
-	DPBM,	 8,	// 0xef - digital port b mode
-	DPCM,	 8,	// 0xf0 - digital port c mode
-	DPDM,	 8,	// 0xf1 - digital port d mode
-	ALFP,	 8,	// 0xf2 - active lfp
-	IMON,	 8,	// 0xf3 - current graphics turbo imon value
-	MMIO,	 8,	// 0xf4 - 64bit mmio support
-
 	/* ChromeOS specific */
 	Offset (0x100),
 	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c
index 9de5126034..0365ea2779 100644
--- a/src/soc/intel/braswell/gfx.c
+++ b/src/soc/intel/braswell/gfx.c
@@ -9,7 +9,6 @@
 #include <drivers/intel/gma/i915.h>
 #include <reg_script.h>
 #include <soc/gfx.h>
-#include <soc/nvs.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 
@@ -50,6 +49,8 @@ static void gfx_init(struct device *dev)
 {
 	printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
 
+	intel_gma_init_igd_opregion();
+
 	if (!CONFIG(RUN_FSP_GOP)) {
 		/* Pre VBIOS Init */
 		gfx_pre_vbios_init(dev);
@@ -60,20 +61,6 @@ static void gfx_init(struct device *dev)
 		/* Post VBIOS Init */
 		gfx_post_vbios_init(dev);
 	}
-	intel_gma_restore_opregion();
-}
-
-uintptr_t gma_get_gnvs_aslb(const void *gnvs)
-{
-	const global_nvs_t *gnvs_ptr = gnvs;
-	return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
-}
-
-void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
-{
-	global_nvs_t *gnvs_ptr = gnvs;
-	if (gnvs_ptr)
-		gnvs_ptr->aslb = aslb;
 }
 
 static void gma_generate_ssdt(const struct device *dev)
diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h
index 412d7b9746..22ea10fe93 100644
--- a/src/soc/intel/braswell/include/soc/nvs.h
+++ b/src/soc/intel/braswell/include/soc/nvs.h
@@ -48,40 +48,7 @@ typedef struct global_nvs_t {
 	u32	cbmc; /* 0x38 - coreboot memconsole */
 	u8	rsvd3[120]; /* 0x3c - 0xb3 - unused */
 
-	/* IGD OpRegion */
-	u32	aslb; /* 0xb4 - IGD OpRegion Base Address */
-	u8	ibtt; /* 0xb8 - IGD boot type */
-	u8	ipat; /* 0xb9 - IGD panel type */
-	u8	itvf; /* 0xba - IGD TV format */
-	u8	itvm; /* 0xbb - IGD TV minor format */
-	u8	ipsc; /* 0xbc - IGD Panel Scaling */
-	u8	iblc; /* 0xbd - IGD BLC configuration */
-	u8	ibia; /* 0xbe - IGD BIA configuration */
-	u8	issc; /* 0xbf - IGD SSC configuration */
-	u8	i409; /* 0xc0 - IGD 0409 modified settings */
-	u8	i509; /* 0xc1 - IGD 0509 modified settings */
-	u8	i609; /* 0xc2 - IGD 0609 modified settings */
-	u8	i709; /* 0xc3 - IGD 0709 modified settings */
-	u8	idmm; /* 0xc4 - IGD Power Conservation */
-	u8	idms; /* 0xc5 - IGD DVMT memory size */
-	u8	if1e; /* 0xc6 - IGD Function 1 Enable */
-	u8	hvco; /* 0xc7 - IGD HPLL VCO */
-	u32	nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */
-	u8	isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */
-	u8	pavp; /* 0xe9 - IGD PAVP data */
-	u8	rsvd12; /* 0xea - rsvd */
-	u8	oscc; /* 0xeb - PCIe OSC control */
-	u8	npce; /* 0xec - native PCIe support */
-	u8	plfl; /* 0xed - platform flavor */
-	u8	brev; /* 0xee - board revision */
-	u8	dpbm; /* 0xef - digital port b mode */
-	u8	dpcm; /* 0xf0 - digital port c mode */
-	u8	dpdm; /* 0xf1 - digital port c mode */
-	u8	alfp; /* 0xf2 - active lfp */
-	u8	imon; /* 0xf3 - current graphics turbo imon value */
-	u8	mmio; /* 0xf4 - 64bit mmio support */
-
-	u8	unused[11];
+	u8	unused[76];
 
 	/* ChromeOS specific (0x100-0xfff) */
 	chromeos_acpi_t chromeos;