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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-06-18 07:39:31 +0300
committerPatrick Georgi <pgeorgi@google.com>2018-06-06 12:29:19 +0000
commit730df3cc43d76d830f6c88441d8bea75b9047a6c (patch)
tree2272d885de331209f3a3b869d84f089cf27e3fde /src/soc/intel/braswell
parent42e422ed66e3057683c4ada29442a36a75e418ba (diff)
arch/x86: Make RELOCATABLE_RAMSTAGE the default
No need to provide an option to try disable this. Also remove explicit ´select RELOCATABLE_MODULES' lines from platform Kconfigs. Change-Id: I5fb169f90331ce37b4113378405323ec856d6fee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/braswell')
-rw-r--r--src/soc/intel/braswell/Kconfig5
1 files changed, 1 insertions, 4 deletions
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 1154c041d1..23e5990d54 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -14,7 +14,7 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_VERSTAGE_X86_32
select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS
- select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE
+ select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
select COLLECT_TIMESTAMPS
select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
@@ -22,8 +22,6 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_SMI_HANDLER
select HAVE_HARD_RESET
select NO_FIXED_XIP_ROM_SIZE
- select RELOCATABLE_MODULES
- select RELOCATABLE_RAMSTAGE
select PARALLEL_MP
select PCIEXP_ASPM
select PCIEXP_CLK_PM
@@ -106,7 +104,6 @@ config DCACHE_RAM_SIZE
config RESET_ON_INVALID_RAMSTAGE_CACHE
bool "Reset the system on S3 wake when ramstage cache invalid."
default n
- depends on RELOCATABLE_RAMSTAGE
help
The haswell romstage code caches the loaded ramstage program
in SMM space. On S3 wake the romstage will copy over a fresh