diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-12-11 17:44:08 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-12-14 11:06:33 +0000 |
| commit | 20c8aa71d140d682f343892b2526001e7f528d49 (patch) | |
| tree | e5744719f875b5e42b61ad8dcb33e6b24276cd3d /src/soc/intel/braswell | |
| parent | 233ae1919b72434ca6cd783c9a946d32953bc7e9 (diff) | |
soc/intel/braswell: Use Kconfig value for TSEG size
SoC selects HAVE_SMI_HANDLER, so TsegSize is always set to 8 MiB. Also,
use SMM_TSEG_SIZE in place of a magic number.
Change-Id: I139e1073426051fea5d30b6ce3dd9746e0e985a2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/braswell')
| -rw-r--r-- | src/soc/intel/braswell/romstage/romstage.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 37ee93cd24..1738679b1e 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -2,6 +2,7 @@ #include <cbmem.h> #include <stdint.h> +#include <commonlib/helpers.h> #include <arch/io.h> #include <device/mmio.h> #include <console/console.h> @@ -113,7 +114,7 @@ void soc_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *upd config = config_of(dev); printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n"); - upd->PcdMrcInitTsegSize = CONFIG(HAVE_SMI_HANDLER) ? 8 : 0; + upd->PcdMrcInitTsegSize = CONFIG_SMM_TSEG_SIZE / MiB; upd->PcdMrcInitMmioSize = 0x800; upd->PcdMrcInitSpdAddr1 = config->PcdMrcInitSpdAddr1; upd->PcdMrcInitSpdAddr2 = config->PcdMrcInitSpdAddr2; |