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| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2021-09-15 16:03:40 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-27 13:33:23 +0000 |
| commit | 658d7c56b8621b1682ce0f2e457e6abce7308851 (patch) | |
| tree | c01eaa76481d7cdcbe00a65c3e03f2576542b615 /src/soc/intel/braswell/xhci.c | |
| parent | b3ffff87dd1e01eb20240279f5d88707475c1428 (diff) | |
mb/google/brya: Correct SSD power sequence
SSD sometimes can't be detected in in warm/cold boot stress.
M.2 spec describes SSD_PREST should be sequenced after power enable.
BUG=b:199822704
TEST=SSD was always discovered in warm/cold boot stress.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If0a9e36cda4dc91bbccec02f39ccb9b658d24056
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/braswell/xhci.c')
0 files changed, 0 insertions, 0 deletions