diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-07-02 11:55:18 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2015-07-06 18:45:23 +0200 |
| commit | acb9c0b6616f96357c303964678eac05177a078d (patch) | |
| tree | 31991144e04b437bb078d8b6a66bc3c081d16da8 /src/soc/intel/braswell/tsc_freq.c | |
| parent | 2bc9cee0f70f133bb31a79b92ea4d982d55d048d (diff) | |
Braswell: Update to end of June.
Remove some CamelCase in acpi.c
Add FSP PcdDvfsEnable configuration parameter.
Add lpc_init and lpc_set_low_power routines.
Remove Braswell reference to make code easier to port to another SOC.
BRANCH=none
BUG=None
TEST=Build and run on cyan
Change-Id: I5063215fc5d19b4a07f3161f76bf3d58e30f6f02
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10768
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/braswell/tsc_freq.c')
| -rw-r--r-- | src/soc/intel/braswell/tsc_freq.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c index e7a1c13f51..34e610f60b 100644 --- a/src/soc/intel/braswell/tsc_freq.c +++ b/src/soc/intel/braswell/tsc_freq.c @@ -20,6 +20,7 @@ #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> +#include <rules.h> #include <soc/msr.h> #include <console/console.h> #if ENV_RAMSTAGE @@ -37,7 +38,7 @@ unsigned long tsc_freq_mhz(void) return (BUS_FREQ_KHZ * ((ia_core_ratios.lo >> 16) & 0x3f)) / 1000; } -#if !defined(__SMM__) +#if !ENV_SMM void set_max_freq(void) { @@ -67,4 +68,4 @@ void set_max_freq(void) wrmsr(MSR_IA32_PERF_CTL, perf_ctl); } -#endif /* __SMM__ */ +#endif /* ENV_SMM */ |