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authorkiwi liu <kiwi.liu@mediatek.corp-partner.google.com>2024-09-11 13:52:17 +0800
committerFelix Held <felix-coreboot@felixheld.de>2024-09-20 12:31:09 +0000
commitc867f746fe011c89c22bd46ebd04b99c4c4aa134 (patch)
tree915c3af2bc1a84317a5085640b07b5cc701a1d0f /src/soc/intel/braswell/southcluster.c
parent7fc3c34dc3d48df5f8f1238575974720cf7b9672 (diff)
soc/mediatek/common: Correct eMMC src clk frequency to 400 MHz
Mediatek SoCs start operating at eMMC clock around 3MHz right after power-on due to wrong src_hz value. In JEDEC spec, eMMC clock needs under 400kHz. When we need to set a clock output frequency, we actually set a frequency division value. Originally, we set the source clock frequency to 50MHz, the target frequency to 400KHz, and get the division value 128. However, the actual source clock frequency is 400MHz, so the final actual output is 400MHz/128=3.125MHz. So we correct source clock frequency to 400MHz for eMMC output clock of 400KHz. BUG=b:356578805 TEST=test boot ok; measure eMMC clock ok; no boot time impact Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381 Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.corp-partner.google.com> Signed-off-by: Kiwi Liu <kiwi.liu@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84298 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
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