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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-06-30 15:25:44 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2015-07-06 18:44:38 +0200 |
| commit | 2bc9cee0f70f133bb31a79b92ea4d982d55d048d (patch) | |
| tree | 812221a06e94ca6cd5853b561b4f83afc68675eb /src/soc/intel/braswell/southcluster.c | |
| parent | 9b8c738942c79c5c34e09d78bbe000cc8a8dfb46 (diff) | |
Braswell: Update the ACPI tables
Build the GNVS pointer and add it to the DSDT.
Add the opregion for GOP support.
Build the SSDT entry and add it to the RSDP.
The arch/x86/boot/acpi.c module adds the HPET entry, remove the
acpi_create_intel_hpet routine.
BRANCH=none
BUG=None
TEST=Build and run on cyan
Change-Id: I8c7ae36b24da583928ad2532f611a855268b51f9
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10748
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/braswell/southcluster.c')
| -rw-r--r-- | src/soc/intel/braswell/southcluster.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 5a3ad9dd31..a3877d6766 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <bootstate.h> #include <cbmem.h> #include "chip.h" @@ -31,6 +32,7 @@ #include <device/pci_ids.h> #include <pc80/mc146818rtc.h> #include <romstage_handoff.h> +#include <soc/acpi.h> #include <soc/iomap.h> #include <soc/irq.h> #include <soc/lpc.h> @@ -449,6 +451,8 @@ static struct device_operations device_ops = { .read_resources = sc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = NULL, + .acpi_inject_dsdt_generator = southcluster_inject_dsdt, + .write_acpi_tables = southcluster_write_acpi_tables, .init = sc_init, .enable = southcluster_enable_dev, .scan_bus = scan_lpc_bus, |