soc/intel/braswell: Clean up

Tested with BUILD_TIMELESS=1, Facebook FBG1701 remains unaffected.

Change-Id: I784a5ddc1a8dcbfb960ce970b28b850244a47773
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39663
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 29 insertions, 54 deletions

diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c
index 584ec88d46..a33c9af96e 100644
--- a/src/soc/intel/braswell/smihandler.c
+++ b/src/soc/intel/braswell/smihandler.c
@@ -87,8 +87,7 @@ static void busmaster_disable_on_bus(int bus)
 			/* If this is a bridge, then follow it. */
 			hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
 			hdr &= 0x7f;
-			if (hdr == PCI_HEADER_TYPE_BRIDGE ||
-			    hdr == PCI_HEADER_TYPE_CARDBUS) {
+			if (hdr == PCI_HEADER_TYPE_BRIDGE || hdr == PCI_HEADER_TYPE_CARDBUS) {
 				unsigned int buses;
 				buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
 				busmaster_disable_on_bus((buses >> 8) & 0xff);
@@ -100,38 +99,24 @@ static void busmaster_disable_on_bus(int bus)
 static void tristate_gpios(uint32_t val)
 {
 	/* Tri-state eMMC */
-	write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
-			SDMMC1_CMD_MMIO_OFFSET, val);
-	write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
-			SDMMC1_D0_MMIO_OFFSET, val);
-	write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
-			SDMMC1_D1_MMIO_OFFSET, val);
-	write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
-			SDMMC1_D2_MMIO_OFFSET, val);
-	write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
-			SDMMC1_D3_MMIO_OFFSET, val);
-	write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
-			MMC1_D4_SD_WE_MMIO_OFFSET, val);
-	write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
-			MMC1_D5_MMIO_OFFSET, val);
-	write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
-			MMC1_D6_MMIO_OFFSET, val);
-	write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
-			MMC1_D7_MMIO_OFFSET, val);
-	write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
-			MMC1_RCLK_OFFSET, val);
+	write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_CMD_MMIO_OFFSET, val);
+	write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D0_MMIO_OFFSET, val);
+	write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D1_MMIO_OFFSET, val);
+	write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D2_MMIO_OFFSET, val);
+	write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D3_MMIO_OFFSET, val);
+	write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_D4_SD_WE_MMIO_OFFSET, val);
+	write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_D5_MMIO_OFFSET, val);
+	write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_D6_MMIO_OFFSET, val);
+	write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_D7_MMIO_OFFSET, val);
+	write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_RCLK_OFFSET, val);
 
 	/* Tri-state HDMI */
-	write32((void *)COMMUNITY_GPNORTH_BASE +
-			HV_DDI2_DDC_SDA_MMIO_OFFSET, val);
-	write32((void *)COMMUNITY_GPNORTH_BASE +
-			HV_DDI2_DDC_SCL_MMIO_OFFSET, val);
+	write32((void *)COMMUNITY_GPNORTH_BASE + HV_DDI2_DDC_SDA_MMIO_OFFSET, val);
+	write32((void *)COMMUNITY_GPNORTH_BASE + HV_DDI2_DDC_SCL_MMIO_OFFSET, val);
 
 	/* Tri-state CFIO 139 and 140 */
-	write32((void *)COMMUNITY_GPSOUTHWEST_BASE +
-			CFIO_139_MMIO_OFFSET, val);
-	write32((void *)COMMUNITY_GPSOUTHWEST_BASE +
-			CFIO_140_MMIO_OFFSET, val);
+	write32((void *)COMMUNITY_GPSOUTHWEST_BASE + CFIO_139_MMIO_OFFSET, val);
+	write32((void *)COMMUNITY_GPSOUTHWEST_BASE + CFIO_140_MMIO_OFFSET, val);
 }
 
 
@@ -156,11 +141,10 @@ static void southbridge_smi_sleep(void)
 	if (slp_typ >= ACPI_S3)
 		elog_gsmi_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
 
-      /* Clear pending GPE events */
+	/* Clear pending GPE events */
 	clear_gpe_status();
 
 	/* Next, do the deed. */
-
 	switch (slp_typ) {
 	case ACPI_S0:
 		printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n");
@@ -183,25 +167,24 @@ static void southbridge_smi_sleep(void)
 		/* Disable all GPE */
 		disable_all_gpe();
 
-		/* also iterates over all bridges on bus 0 */
+		/* Also iterates over all bridges on bus 0 */
 		busmaster_disable_on_bus(0);
 		break;
 	default:
 		printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n");
 		break;
 	}
+
 	/* Clear pending wake status bit to avoid immediate wake */
-	write32((void *)(0xfed88000 + 0x0200),
-		read32((void *)(0xfed88000 + 0x0200)));
+	write32((void *)(0xfed88000 + 0x0200), read32((void *)(0xfed88000 + 0x0200)));
 
 	/* Tri-state specific GPIOS to avoid leakage during S3/S5 */
 	if ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5))
 		tristate_gpios(PAD_CONTROL_REG0_TRISTATE);
 
 	/*
-	 * Write back to the SLP register to cause the originally intended
-	 * event again. We need to set BIT13 (SLP_EN) though to make the
-	 * sleep happen.
+	 * Write back to the SLP register to cause the originally intended event again.
+	 * We need to set BIT13 (SLP_EN) though to make the sleep happen.
 	 */
 	enable_pm1_control(SLP_EN);
 
@@ -222,9 +205,8 @@ static void southbridge_smi_sleep(void)
 }
 
 /*
- * Look for Synchronous IO SMI and use save state from that
- * core in case we are not running on the same core that
- * initiated the IO transaction.
+ * Look for Synchronous IO SMI and use save state from that core in case
+ * we are not running on the same core that initiated the IO transaction.
  */
 static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd)
 {
@@ -261,8 +243,7 @@ static void southbridge_smi_gsmi(void)
 {
 	u32 *ret, *param;
 	uint8_t sub_command;
-	em64t100_smm_state_save_area_t *io_smi =
-		smi_apmc_find_state_save(APM_CNT_ELOG_GSMI);
+	em64t100_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_ELOG_GSMI);
 
 	if (!io_smi)
 		return;
@@ -281,8 +262,7 @@ static void southbridge_smi_gsmi(void)
 static void southbridge_smi_store(void)
 {
 	u8 sub_command, ret;
-	em64t100_smm_state_save_area_t *io_smi =
-		smi_apmc_find_state_save(APM_CNT_SMMSTORE);
+	em64t100_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_SMMSTORE);
 	uint32_t reg_ebx;
 
 	if (!io_smi)
@@ -333,8 +313,7 @@ static void southbridge_smi_apmc(void)
 		break;
 	case APM_CNT_GNVS_UPDATE:
 		if (smm_initialized) {
-			printk(BIOS_DEBUG,
-			       "SMI#: SMM structures already initialized!\n");
+			printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
 			return;
 		}
 		state = smi_apmc_find_state_save(reg8);
@@ -362,12 +341,9 @@ static void southbridge_smi_pm1(void)
 {
 	uint16_t pm1_sts = clear_pm1_status();
 
-	/*
-	 * While OSPM is not active, poweroff immediately
-	 * on a power button event.
-	 */
+	/* While OSPM is not active, poweroff immediately on a power button event */
 	if (pm1_sts & PWRBTN_STS) {
-		/* power button pressed */
+		/* Power button pressed */
 		elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON);
 		disable_pm1_control(-1UL);
 		enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
@@ -463,8 +439,7 @@ void southbridge_smi_handler(void)
 			southbridge_smi[i]();
 		} else {
 			printk(BIOS_DEBUG,
-			       "SMI_STS[%d] occurred, but no "
-			       "handler available.\n", i);
+			       "SMI_STS[%d] occurred, but no handler available.\n", i);
 		}
 	}