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authorElyes HAOUAS <ehaouas@noos.fr>2020-04-29 10:28:20 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-05-01 16:37:13 +0000
commit066e61f3ea1f65012b14467412e6b17351c87dc6 (patch)
tree0536c4c8d9059f1b765cc2388f6d6974d0486d54 /src/soc/intel/braswell/smihandler.c
parentad87d1c8b9285cfed47b3ec060be520a467189ff (diff)
soc/intel/braswell: Fix 16-bit read/write PCI_COMMAND register
Change-Id: Ie213b8c08e2d2b33a1dc1fda632163160d1cd70e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/braswell/smihandler.c')
-rw-r--r--src/soc/intel/braswell/smihandler.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c
index e96f452341..188c14ee42 100644
--- a/src/soc/intel/braswell/smihandler.c
+++ b/src/soc/intel/braswell/smihandler.c
@@ -59,7 +59,7 @@ static void busmaster_disable_on_bus(int bus)
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
- u32 reg32;
+ u16 reg16;
pci_devfn_t dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID);
@@ -69,9 +69,9 @@ static void busmaster_disable_on_bus(int bus)
continue;
/* Disable Bus Mastering for this one device */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 &= ~PCI_COMMAND_MASTER;
- pci_write_config32(dev, PCI_COMMAND, reg32);
+ reg16 = pci_read_config16(dev, PCI_COMMAND);
+ reg16 &= ~PCI_COMMAND_MASTER;
+ pci_write_config16(dev, PCI_COMMAND, reg16);
/* If this is a bridge, then follow it. */
hdr = pci_read_config8(dev, PCI_HEADER_TYPE);