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| author | Kevin Chiu <Kevin.Chiu@quantatw.com> | 2016-06-30 14:50:52 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-09-08 21:09:48 +0000 |
| commit | 348a6d519c9b42f0bbe211f8e550d06aa7d5c210 (patch) | |
| tree | 79c1a1f7b702ac202800d4d3e97041df410a2613 /src/soc/intel/braswell/scc.c | |
| parent | 2c8ac228739373f6f03c70ffcc263bd23ba01ac6 (diff) | |
soc/intel/braswell: add USB2 PHY PERPORTRXISET UPD
Adapted from Chromium commits 59938a0, 5a4ea6e, 88999de.
Add UPD to config USB2 PERPORTRXISET for D-stepping BSW SoC.
Ensure PerPortRXISet UPD offsets align with FSP.
Ensure UPD values not defined in devicetree.cb are referred from *.dsc.
Original-Change-Id: Ib0cdee47692e492a78c34e2dd192447b92253e35
Original-Change-Id: If0d8419d4c70864bd385b5699e0e6d1ec515d26a
Original-Change-Id: I3a1d688282303e8c367620ac8bb3e2cba7ab3dcf
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
Change-Id: I87eda6ea6688931f1a1b069c38ffc515398ad396
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/braswell/scc.c')
0 files changed, 0 insertions, 0 deletions