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| author | T.H. Lin <T.H_Lin@quantatw.com> | 2016-10-26 17:24:33 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-08-25 18:58:48 +0000 |
| commit | c648aac31d5de2149b2821db384920f5da0f08d2 (patch) | |
| tree | 4e37f8f1f29b65642fe206e01d811bcbeaf485c4 /src/soc/intel/braswell/scc.c | |
| parent | 77c13f03f5291958b933059eeeb99f9c0660552a (diff) | |
google/cyan: Add 2nd source memory (Micro/Samsung)
Cherry-pick from Chromium commit 3b578ef.
Cyan board use new 2nd source memory (Micro/Samsung)
Original-Change-Id: I6f4e8438faede7ac742776a622c265922e498898
Original-Signed-off-by: T.H. Lin <T.H_Lin@quantatw.com>
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Change-Id: Ie2febe4de57c00c269def15d57f2b5a6f0f378aa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/braswell/scc.c')
0 files changed, 0 insertions, 0 deletions