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| author | T.H. Lin <T.H_Lin@quantatw.com> | 2016-12-13 15:43:57 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-08-25 18:59:06 +0000 |
| commit | aec5e663eb8581aeaadd55661c37bde948a7015e (patch) | |
| tree | 42b1a1f29d776ad3fafe10c5f163592c167e1df2 /src/soc/intel/braswell/scc.c | |
| parent | c648aac31d5de2149b2821db384920f5da0f08d2 (diff) | |
google/cyan: Add 2nd source memory 2-channel 4G (Micro/Samsung)
Cherry-pick from Chromium commit 7f0cdf0.
Cyan board add 4G DDR3L 2nd source memory (Micro/Samsung)
Original-Change-Id: I12f82082d8227e61a97ce0a001d7d2b1f6613e06
Original-Signed-off-by: T.H. Lin <T.H_Lin@quantatw.com>
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Change-Id: Ieca7201346414d7a962f9619dbe846c67c0f02d6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/braswell/scc.c')
0 files changed, 0 insertions, 0 deletions