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authorKyösti Mälkki <kyosti.malkki@gmail.com>2021-01-12 17:46:30 +0200
committerPatrick Georgi <pgeorgi@google.com>2021-01-27 10:25:03 +0000
commit4abc73183134def757c553aa4eb195fffa824100 (patch)
treee6fa253f8e7dc46e80a0a33ea903b4fe0be83419 /src/soc/intel/braswell/scc.c
parentaeffa86cc551110b62074fa6302f4960d87a9a8c (diff)
ACPI: Separate device_nvs_t
Remove typedef device_nvs_t and move struct device_nvs outside of global_nvs. Also remove padding and the reserve for chromeos_acpi_t. Change-Id: I878746b1f0f9152a27dc58e373d58115e2dff22c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/braswell/scc.c')
-rw-r--r--src/soc/intel/braswell/scc.c15
1 files changed, 5 insertions, 10 deletions
diff --git a/src/soc/intel/braswell/scc.c b/src/soc/intel/braswell/scc.c
index 45ce8de982..c6d4f5201e 100644
--- a/src/soc/intel/braswell/scc.c
+++ b/src/soc/intel/braswell/scc.c
@@ -5,27 +5,22 @@
#include <device/device.h>
#include <device/pci.h>
#include <soc/iosf.h>
-#include <soc/nvs.h>
+#include <soc/device_nvs.h>
#include <soc/ramstage.h>
void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
{
struct resource *bar;
- struct global_nvs *gnvs;
-
- /* Find ACPI NVS to update BARs */
- gnvs = acpi_get_gnvs();
- if (!gnvs)
- return;
+ struct device_nvs *dev_nvs = acpi_get_device_nvs();
/* Save BAR0 and BAR1 to ACPI NVS */
bar = find_resource(dev, PCI_BASE_ADDRESS_0);
if (bar)
- gnvs->dev.scc_bar0[nvs_index] = bar->base;
+ dev_nvs->scc_bar0[nvs_index] = bar->base;
bar = find_resource(dev, PCI_BASE_ADDRESS_2);
if (bar)
- gnvs->dev.scc_bar1[nvs_index] = bar->base;
+ dev_nvs->scc_bar1[nvs_index] = bar->base;
/* Device is enabled in ACPI mode */
- gnvs->dev.scc_en[nvs_index] = 1;
+ dev_nvs->scc_en[nvs_index] = 1;
}