diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-10-15 16:17:58 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-10-27 15:19:12 +0100 |
| commit | 66208bd3d5203ccaf052c3e3663df702d367e4a7 (patch) | |
| tree | 400981ed811c1dcd2ae415fad967bd98c5a4cff4 /src/soc/intel/braswell/romstage | |
| parent | 94b856ef9afaca880909d22b24d5443408c47920 (diff) | |
FSP 1.1: Replace soc_ prefix with fsp_
Rename soc_display_upd_value to fsp_display_upd_value since the routine
was moved from src/soc/intel/common into src/drivers/intel/fsp1_1.
BRANCH=none
BUG=None
TEST=Build and run on Kunimitsu
Change-Id: Ifadf9dcdf8c81f8de961e074226c349fb9634792
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 95238782702999a178989467694ac1f15c079615
Original-Change-Id: Ibd26ea41bd5c7a54ecd3c237f7fb7bad6dbf7d8a
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/306351
Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12157
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Diffstat (limited to 'src/soc/intel/braswell/romstage')
| -rw-r--r-- | src/soc/intel/braswell/romstage/romstage.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 0b1eab5f04..13b481f628 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -223,28 +223,28 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, { /* Display the parameters for MemoryInit */ printk(BIOS_SPEW, "UPD values for MemoryInit:\n"); - soc_display_upd_value("PcdMrcInitTsegSize", 2, + fsp_display_upd_value("PcdMrcInitTsegSize", 2, old->PcdMrcInitTsegSize, new->PcdMrcInitTsegSize); - soc_display_upd_value("PcdMrcInitMmioSize", 2, + fsp_display_upd_value("PcdMrcInitMmioSize", 2, old->PcdMrcInitMmioSize, new->PcdMrcInitMmioSize); - soc_display_upd_value("PcdMrcInitSpdAddr1", 1, + fsp_display_upd_value("PcdMrcInitSpdAddr1", 1, old->PcdMrcInitSpdAddr1, new->PcdMrcInitSpdAddr1); - soc_display_upd_value("PcdMrcInitSpdAddr2", 1, + fsp_display_upd_value("PcdMrcInitSpdAddr2", 1, old->PcdMrcInitSpdAddr2, new->PcdMrcInitSpdAddr2); - soc_display_upd_value("PcdMemChannel0Config", 1, + fsp_display_upd_value("PcdMemChannel0Config", 1, old->PcdMemChannel0Config, new->PcdMemChannel0Config); - soc_display_upd_value("PcdMemChannel1Config", 1, + fsp_display_upd_value("PcdMemChannel1Config", 1, old->PcdMemChannel1Config, new->PcdMemChannel1Config); - soc_display_upd_value("PcdMemorySpdPtr", 4, + fsp_display_upd_value("PcdMemorySpdPtr", 4, old->PcdMemorySpdPtr, new->PcdMemorySpdPtr); - soc_display_upd_value("PcdIgdDvmt50PreAlloc", 1, + fsp_display_upd_value("PcdIgdDvmt50PreAlloc", 1, old->PcdIgdDvmt50PreAlloc, new->PcdIgdDvmt50PreAlloc); - soc_display_upd_value("PcdApertureSize", 1, + fsp_display_upd_value("PcdApertureSize", 1, old->PcdApertureSize, new->PcdApertureSize); - soc_display_upd_value("PcdGttSize", 1, + fsp_display_upd_value("PcdGttSize", 1, old->PcdGttSize, new->PcdGttSize); - soc_display_upd_value("PcdLegacySegDecode", 1, + fsp_display_upd_value("PcdLegacySegDecode", 1, old->PcdLegacySegDecode, new->PcdLegacySegDecode); - soc_display_upd_value("PcdDvfsEnable", 1, + fsp_display_upd_value("PcdDvfsEnable", 1, old->PcdDvfsEnable, new->PcdDvfsEnable); } |